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Xilinx PCI-X v5.1 Installing Your License File, Full License, Direct Download, Licensing the Core

Models: PCI-X v5.1

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Chapter 2: Licensing the Core

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Chapter 2: Licensing the Core

Full License

The Full license is provided when you purchase the core, and provides full access to all core functionality both in simulation and in hardware, including:

•Gate-level functional simulation support.

•Back annotated gate-level simulation support.

•Full implementation support including place and route and bitstream generation.

•Full functionality in the programmed device with no time-outs.

Obtaining a Full License

To obtain a Full license, you must purchase the core. After purchase, a full license can be downloaded from the product lounge. To create and download a license file for use with the CORE Generator software, do the following:

1.After purchase, you will receive a letter containing a serial number, which is used to register for access to the lounge; a secured area of the product page.

Go to www.xilinx.com/pci/index.htm and choose the appropriate link to gain access.

2.From the product page, click Register to request access to the lounge. Xilinx will review your access request and typically grants access to the lounge in 48 hours. (Contact Xilinx Customer Service if you need faster turnaround.)

3.After you receive confirmation of lounge access, click Access Lounge from the product page and log in.

4.From the lounge, a link at the top of the initial page allows you to generate a license. Click this link and follow the instructions to fill out the license request form; then click Submit to generate the license. An e-mail containing license and installation instructions will be sent to you immediately.

Direct Download

A CORE Generator license is not required when performing a direct download of the

Initiator/Target core for PCI-X core.

Installing Your License File

After selecting a license option, an email will be sent to you that includes instructions for installing your license file. In addition, information about advanced licensing options and technical support is provided.

16	www.xilinx.com	PCI-X v5.1 165 Getting Started Guide
		UG158 March 24, 2008

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Xilinx PCI-X v5.1 manual Installing Your License File, Direct Download, Obtaining a Full License, Licensing the Core

Contents

LogiCORE IP Initiator/Target v5.1 for PCI-X UG158 March 24Getting Started Guide Revision VersionPCI-X v5.1 165 Getting Started Guide UG158 March 24 Revision Versionug000preface.fm to “Guide.” Updated tools for IP0K release VersionRevision 10/10/07Table of Contents Preface About This GuideChapter 1 Getting Started Chapter 2 Licensing the CoreChapter 6 Implementing a Design Chapter 7 Timing SimulationVerilog VHDL Exemplar LeonardoSpectrum Xilinx XST ISE FoundationSchedule of Figures Chapter 1 Getting Started Chapter 2 Licensing the CoreChapter 4 Functional Simulation Chapter 5 Synthesizing a Design Chapter 6 Implementing a Design Chapter 7 Timing SimulationPCI-X v5.1 165 Getting Started Guide UG158 March 24About This Guide Guide ContentsPreface Conventions TypographicalPreface About This Guide ConventionOnline Document ConventionsSee “Additional Resources” Blue textPCI-X v5.1 165 Getting Started Guide Preface About This GuideUG158 March Getting Started ChapterSystem Requirements About the Example DesignAdditional Documentation Technical SupportFeedback Core Interface for PCI-XLicensing the Core Before you BeginLicensing Options Full System Hardware EvaluationInstalling Your License File Full LicenseDirect Download Obtaining a Full LicenseFamily Specific Considerations Design SupportTable 3-1 Device and Interface Selection Supported DeviceChapter 3 Family Specific Considerations Wrapper FileTable 3-1 Device and Interface Selection Supported DeviceDesign Support Table 3-1 Device and Interface Selection Wrapper FileSupported Device Bus TypeWrapper Files Constraints FilesChapter 3 Family Specific Considerations Table 3-1 Device and Interface SelectionConfiguration Pins Device InitializationBus Width Detection Bus Mode DetectionBus Clock Usage Table 3-2 Bitstream RequirementsDesired System Interface Implementation Bitstreams3.6 volts, as allowed by the PCI Local Bus Specification Electrical ComplianceElectrical Compliance Figure 3-1 PCI/PCI-X Output Driver VCCO GenerationInput Delay Buffers Chapter 3 Family Specific ConsiderationsGenerating Bitstreams Generating BitstreamsPCI-X v5.1 165 Getting Started Guide Chapter 3 Family Specific ConsiderationsUG158 March 24 Cadence IUS Functional SimulationChapter Verilog Mentor Graphics ModelSimChapter 4 Functional Simulation VHDL Mentor Graphics ModelSimChapter 4 Functional Simulation vlib simprimSynthesizing a Design Synplicity SynplifyFigure 5-1 Create a New Project ChapterChapter 5 Synthesizing a Design Figure 5-2 Main Project WindowFigure 5-3 Files to Add Virtex Library Synplicity SynplifyFigure 5-4 Files to Add LogiCORE Files Figure 5-5 Files to Add User Application Figure 5-6 Source Files in Main Project WindowChapter 5 Synthesizing a Design 7. Navigate to the source directory Figure 5-5, select the cfgtests.v, pcixtop.v, and userapp.v files, and then click AddFigure 5-7 Options for Implementation Device Synplicity Synplify10. Click Change Result File to display the EDIF Result File dialog box then move the to following directory Figure 5-8 Options for Implementation Options/ConstraintsFigure 5-9 Create a New Project Install Path/vhdl/example/synthesisVHDL Chapter 5 Synthesizing a DesignFigure 5-10 Main Project Window Figure 5-11 Files to Add Virtex LibrarySynplicity Synplify 3. Click OK to exit the dialog and return to the project window FigureFigure 5-12 Files to Add LogiCORE Files Figure 5-13 Files to Add User ApplicationInstall Path/vhdl/src/xpci Install Path/vhdl/example/sourceSynplicity Synplify Figure 5-14 Main Project Window8. In the Source Files list, view the list of newly added source files by double-clicking the flowtest/vhdl folder if it is not already open. Drag to reorder the source files in the hierarchical order shown in Figure Figure 5-15 Options for Implementation Device Exemplar LeonardoSpectrumChapter 5 Synthesizing a Design Xilinx XST Xilinx XSTPCI-X v5.1 165 Getting Started Guide Chapter 5 Synthesizing a DesignUG158 March 24 ISE Foundation Implementing a DesignChapter Chapter 6 Implementing a Design Timing Simulation cd Install Path/verilog/example/postsim cp ../xilinx/*.vChapter Cadence IUSChapter 7 Timing Simulation Mentor Graphics ModelSimVerilog VHDLInstall Path/vhdl/example/postsim Mentor Graphics ModelSim