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PCI-X v5.1
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Synthesizing a Design
Models:
PCI-X v5.1
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Input Delay Buffers
Configuration Pins
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Chapter 5:
Synthesizing a Design
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PCI-X
v5.1 165 Getting Started Guide
UG158 March 24, 2008
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Contents
LogiCORE IP Initiator/Target v5.1 for PCI-X
UG158 March 24
PCI-X v5.1 165 Getting Started Guide UG158 March 24
Version Revision
Ug000preface.fm to Guide
Version Revision
Table of Contents
Implementing a Design
Schedule of Figures
8Options for Implementation Options/Constraints
PCI-X v5.1 165 Getting Started Guide
Guide Contents
About This Guide
Preface About This Guide
Conventions
Typographical
Convention Meaning or Use Example
Online Document
Conventions
Preface About This Guide
Getting Started
System Requirements
About the Example Design
Feedback
Additional Documentation
Technical Support
Core Interface for PCI-X
Licensing Options
Licensing the Core
Before you Begin
Full System Hardware Evaluation
Direct Download
Installing Your License File
Full License
Licensing the Core
Family Specific Considerations
Design Support
Simulation
Virtex-4 Devices
Wrapper Files
Device Initialization
Configuration Pins
Bus Mode Detection
Bus Width Detection
Bus Clock Usage
Family Specific Considerations
Electrical Compliance
Electrical Compliance
Input Delay Buffers
Generating Bitstreams
Generating Bitstreams
Family Specific Considerations
Functional Simulation
Cadence IUS
Mentor Graphics ModelSim
Verilog
Functional Simulation
Install Path/verilog/example/funcsim
Mentor Graphics ModelSim
To run the simulation, type the following do modelsim.do
Synthesizing a Design
Synplicity Synplify
Synthesizing a Design
2Main Project Window
Synplicity Synplify
3Files to Add Virtex Library
5Files to Add User Application
7Options for Implementation Device
9Create a New Project
10Main Project Window
12Files to Add LogiCORE Files
14Main Project Window
Exemplar LeonardoSpectrum
15Options for Implementation Device
Xilinx XST
Xilinx XST
Synthesizing a Design
Implementing a Design
ISE Foundation
Implementing a Design
Timing Simulation
Timing Simulation
Install Path/vhdl/example/postsim
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