R
Chapter 7
Timing Simulation
This chapter describes the use of supported timing simulation tools using the Userapp example design. If you are using a design with reference clocks, substitute pcix_top with pcix_top_r and test_tb with test_tb_r.
Supported timing simulation tools include
•Cadence IUS v6.1
•Mentor Graphics ModelSim v6.3c
Note: The stimulus source file delivered with the example design
(source/stimulus.hdl) simulates in both PCI and
Cadence IUS
Before attempting timing simulation, ensure that the IUS environment is properly configured for use.
1.Navigate to the timing simulation directory and copy the back annotated timing models from the implementation directory:
cd <Install Path>/verilog/example/post_sim cp ../xilinx/*.v ./
cp ../xilinx/*.sdf ./
2.Edit the test_tb.f file. This file lists command line arguments for IUS, and is shown below:
../source/stimulus.v
../source/test_tb.v
../source/busrec.v
./pcix_top_s_routed.v +libext+.vmd+.v
Modify the library search path by changing <Xilinx Install Path> to match the Xilinx installation directory. Save the file.
3.To run the IUS simulation, type the following: ncverilog
IUS processes the simulation files and exits. The test bench prints status messages to the console. After the simulation completes, view the ncverilog.log file to check for errors.
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UG158 March 24, 2008
