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Xilinx PCI-X v5.1 manual Synplicity Synplify, 3 Files to Add Virtex Library

Models: PCI-X v5.1

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Synplicity Synplify

5.Navigate to the virtex.v file (Figure 5-3); then click Add to move this source file into the Files To Add list.

Figure 5-3:Files to Add (Virtex Library)

The next files are located in:

<Install Path>/verilog/src/xpci

6.Navigate to the xpci directory (Figure 5-4), select the simulation model and the wrapper files (pcix_core.v and pcix_lc.v), and click Add to move these files into the Files To Add list. (Ctrl + click to select multiple files.)

Figure 5-4:Files to Add (LogiCORE Files)

The final set of design files (the user application) is located in:

<Install Path>/verilog/example/source

PCI-X v5.1 165 Getting Started Guide

www.xilinx.com

UG158 March 24, 2008

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Xilinx PCI-X v5.1 manual Synplicity Synplify, 3 Files to Add Virtex Library, 4 Files to Add LogiCORE Files

Contents

UG158 March 24 LogiCORE IP Initiator/Target v5.1 for PCI-XGetting Started Guide Version RevisionPCI-X v5.1 165 Getting Started Guide UG158 March 24 Version Revisionug000preface.fm to “Guide.” Version Updated tools for IP0K releaseRevision 10/10/07Preface About This Guide Table of ContentsChapter 1 Getting Started Chapter 2 Licensing the CoreChapter 7 Timing Simulation Chapter 6 Implementing a DesignVerilog VHDL Exemplar LeonardoSpectrum Xilinx XST ISE FoundationChapter 1 Getting Started Chapter 2 Licensing the Core Schedule of FiguresChapter 4 Functional Simulation Chapter 5 Synthesizing a Design Chapter 6 Implementing a Design Chapter 7 Timing SimulationUG158 March 24 PCI-X v5.1 165 Getting Started GuideGuide Contents About This GuidePreface Typographical ConventionsPreface About This Guide ConventionConventions Online DocumentSee “Additional Resources” Blue textPreface About This Guide PCI-X v5.1 165 Getting Started GuideUG158 March 24 Chapter Getting StartedSystem Requirements About the Example DesignTechnical Support Additional DocumentationFeedback Core Interface for PCI-XBefore you Begin Licensing the CoreLicensing Options Full System Hardware EvaluationFull License Installing Your License FileDirect Download Obtaining a Full LicenseDesign Support Family Specific ConsiderationsTable 3-1 Device and Interface Selection Supported DeviceWrapper File Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Supported DeviceWrapper File Design Support Table 3-1 Device and Interface SelectionSupported Device Bus TypeConstraints Files Wrapper FilesChapter 3 Family Specific Considerations Table 3-1 Device and Interface SelectionBus Mode Detection Configuration PinsDevice Initialization Bus Width DetectionTable 3-2 Bitstream Requirements Bus Clock UsageDesired System Interface Implementation BitstreamsElectrical Compliance 3.6 volts, as allowed by the PCI Local Bus SpecificationElectrical Compliance Figure 3-1 PCI/PCI-X Output Driver VCCO GenerationChapter 3 Family Specific Considerations Input Delay BuffersGenerating Bitstreams Generating BitstreamsChapter 3 Family Specific Considerations PCI-X v5.1 165 Getting Started GuideUG158 March 24 Functional Simulation Cadence IUSChapter Mentor Graphics ModelSim VerilogChapter 4 Functional Simulation Mentor Graphics ModelSim VHDLvlib simprim Chapter 4 Functional SimulationSynplicity Synplify Synthesizing a DesignFigure 5-1 Create a New Project ChapterFigure 5-2 Main Project Window Chapter 5 Synthesizing a DesignSynplicity Synplify Figure 5-3 Files to Add Virtex LibraryFigure 5-4 Files to Add LogiCORE Files Figure 5-6 Source Files in Main Project Window Figure 5-5 Files to Add User ApplicationChapter 5 Synthesizing a Design 7. Navigate to the source directory Figure 5-5, select the cfgtests.v, pcixtop.v, and userapp.v files, and then click AddSynplicity Synplify Figure 5-7 Options for Implementation Device10. Click Change Result File to display the EDIF Result File dialog box then move the to following directory Figure 5-8 Options for Implementation Options/ConstraintsInstall Path/vhdl/example/synthesis Figure 5-9 Create a New ProjectVHDL Chapter 5 Synthesizing a DesignFigure 5-11 Files to Add Virtex Library Figure 5-10 Main Project WindowSynplicity Synplify 3. Click OK to exit the dialog and return to the project window FigureFigure 5-13 Files to Add User Application Figure 5-12 Files to Add LogiCORE FilesInstall Path/vhdl/src/xpci Install Path/vhdl/example/sourceFigure 5-14 Main Project Window Synplicity Synplify8. In the Source Files list, view the list of newly added source files by double-clicking the flowtest/vhdl folder if it is not already open. Drag to reorder the source files in the hierarchical order shown in Figure Exemplar LeonardoSpectrum Figure 5-15 Options for Implementation DeviceChapter 5 Synthesizing a Design Xilinx XST Xilinx XSTChapter 5 Synthesizing a Design PCI-X v5.1 165 Getting Started GuideUG158 March 24 Implementing a Design ISE FoundationChapter Chapter 6 Implementing a Design cd Install Path/verilog/example/postsim cp ../xilinx/*.v Timing SimulationChapter Cadence IUSMentor Graphics ModelSim Chapter 7 Timing SimulationVerilog VHDLMentor Graphics ModelSim Install Path/vhdl/example/postsim