Xilinx PCI-X v5.1 manual Synthesizing a Design, Synplicity Synplify

R

Chapter 5

Synthesizing a Design

This chapter describes the use of supported synthesis tools using the Userapp example design for step-by-step instructions and illustrations. If you are using a design with reference clocks, substitute pcix_top with pcix_top_r and test_tb with test_tb_r.

Supported synthesis tools include

•Synplicity Synplify

•Exemplar LeonardoSpectrum

•Xilinx XST

Each section in this chapter illustrates how to synthesize the example design for dual- mode operation with a single bitstream. The synthesis flow for other configurations is identical.

Synplicity Synplify

Before synthesizing a design, ensure that the Synplicity Synplify environment is properly configured.

Verilog

1.Start Synplify and choose File > New (Figure 5-1), or click the new file icon on the tool bar.

The New dialog appears.

Figure 5-1:Create a New Project

PCI-X v5.1 165 Getting Started Guide www.xilinx.com 31

UG158 March 24, 2008