Device Initialization
R
Device Initialization
Immediately after FPGA configuration, both the core interface and the user application are initialized by the startup mechanism present in all Virtex devices. During normal operation, the assertion of RST# on the
Typically, the user application must be initialized each time the core interfacee is initialized. In this case, use the RST output of the core interface as the asynchronous reset signal for the user application. If part of the user application requires an initialization capability that is asynchronous to
Note that these reset schemes require the use of routing resources to distribute reset signals, since the global resource is not used. The use of the global reset resource is not recommended.
Configuration Pins
Designers should be aware that
Bus Width Detection
A core interface that provides a
Bus Mode Detection
A core interface that provides backward compatibility with PCI mode must determine whether it is in
The core interface targeting
For designs that use multiple bitstreams, the RTR output of the core interface will assert following the deassertion of the bus reset signal if the interface recognizes that the incorrect
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UG158 March 24, 2008