Online Document, Conventions | Xilinx PCI-X v5.1 instruction

Conventions

R

Online Document

The following conventions are used in this document:

	Convention	Meaning or Use	Example

		Cross-reference link to a	See “Additional Resources”
		Cross-reference link to a	for details.
	Blue text	location in the current	for details.
	Blue text	location in the current	See “Title Formats” in Chapter
		document	See “Title Formats” in Chapter
		document	1 for details.
			1 for details.

	Blue, underlined text	Hyperlink to a website (URL)	Go to http://www.xilinx.com
	Blue, underlined text	Hyperlink to a website (URL)	for the latest speed files.
			for the latest speed files.

PCI-X v5.1 165 Getting Started Guide

www.xilinx.com

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UG158 March 24, 2008

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Xilinx PCI-X v5.1 manual Online Document, Conventions

Contents

UG158 March 24 LogiCORE IP Initiator/Target v5.1 for PCI-X Version Revision PCI-X v5.1 165 Getting Started Guide UG158 March 24 Ug000preface.fm to Guide Version Revision Table of Contents Implementing a Design 8Options for Implementation Options/Constraints Schedule of Figures PCI-X v5.1 165 Getting Started Guide About This Guide Guide Contents Convention Meaning or Use Example ConventionsTypographical Preface About This Guide Conventions Online Document Preface About This Guide About the Example Design Getting StartedSystem Requirements Core Interface for PCI-X Additional DocumentationTechnical Support Feedback Full System Hardware Evaluation Licensing the CoreBefore you Begin Licensing Options Licensing the Core Installing Your License FileFull License Direct Download Design Support Family Specific Considerations Simulation Virtex-4 Devices Wrapper Files Bus Width Detection Configuration PinsBus Mode Detection Device Initialization Family Specific Considerations Bus Clock Usage Electrical Compliance Electrical Compliance Input Delay Buffers Generating Bitstreams Generating Bitstreams Family Specific Considerations Cadence IUS Functional Simulation Functional Simulation Mentor Graphics ModelSimVerilog Mentor Graphics ModelSim Install Path/verilog/example/funcsim To run the simulation, type the following do modelsim.do Synplicity Synplify Synthesizing a Design 2Main Project Window Synthesizing a Design 3Files to Add Virtex Library Synplicity Synplify 5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window 15Options for Implementation Device Exemplar LeonardoSpectrum Xilinx XST Xilinx XST Synthesizing a Design ISE Foundation Implementing a Design Implementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim