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Xilinx PCI-X v5.1 Online Document, Conventions, See “Additional Resources”, Blue text, Example

Models: PCI-X v5.1

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Conventions

Online Document

The following conventions are used in this document:

Convention	Meaning or Use	Example

	Cross-reference link to a	See “Additional Resources”
	Cross-reference link to a	for details.
Blue text	location in the current	for details.
Blue text	location in the current	See “Title Formats” in Chapter
	document	See “Title Formats” in Chapter
	document	1 for details.
		1 for details.

Blue, underlined text	Hyperlink to a website (URL)	Go to http://www.xilinx.com
Blue, underlined text	Hyperlink to a website (URL)	for the latest speed files.
		for the latest speed files.

PCI-X v5.1 165 Getting Started Guide

www.xilinx.com

UG158 March 24, 2008

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Xilinx PCI-X v5.1 Online Document, Conventions, See “Additional Resources”, Blue text, See “Title Formats” in Chapter

Contents

Getting Started Guide UG158 March 24LogiCORE IP Initiator/Target v5.1 for PCI-X PCI-X v5.1 165 Getting Started Guide UG158 March 24 VersionRevision ug000preface.fm to “Guide.” VersionRevision 10/10/07 Updated tools for IP0K releaseVersion RevisionChapter 2 Licensing the Core Table of ContentsPreface About This Guide Chapter 1 Getting StartedISE Foundation Chapter 6 Implementing a DesignChapter 7 Timing Simulation Verilog VHDL Exemplar LeonardoSpectrum Xilinx XSTChapter 6 Implementing a Design Chapter 7 Timing Simulation Schedule of FiguresChapter 1 Getting Started Chapter 2 Licensing the Core Chapter 4 Functional Simulation Chapter 5 Synthesizing a DesignUG158 March 24 PCI-X v5.1 165 Getting Started GuidePreface Guide ContentsAbout This Guide Convention ConventionsTypographical Preface About This GuideBlue text Online DocumentConventions See “Additional Resources”UG158 March 24 Preface About This GuidePCI-X v5.1 165 Getting Started Guide About the Example Design Getting StartedChapter System RequirementsCore Interface for PCI-X Additional DocumentationTechnical Support FeedbackFull System Hardware Evaluation Licensing the CoreBefore you Begin Licensing OptionsObtaining a Full License Installing Your License FileFull License Direct DownloadSupported Device Family Specific ConsiderationsDesign Support Table 3-1 Device and Interface SelectionSupported Device Chapter 3 Family Specific ConsiderationsWrapper File Table 3-1 Device and Interface SelectionBus Type Design Support Table 3-1 Device and Interface SelectionWrapper File Supported DeviceTable 3-1 Device and Interface Selection Wrapper FilesConstraints Files Chapter 3 Family Specific ConsiderationsBus Width Detection Configuration PinsBus Mode Detection Device InitializationBitstreams Bus Clock UsageTable 3-2 Bitstream Requirements Desired System Interface ImplementationFigure 3-1 PCI/PCI-X Output Driver VCCO Generation 3.6 volts, as allowed by the PCI Local Bus SpecificationElectrical Compliance Electrical ComplianceChapter 3 Family Specific Considerations Input Delay BuffersGenerating Bitstreams Generating BitstreamsUG158 March 24 Chapter 3 Family Specific ConsiderationsPCI-X v5.1 165 Getting Started Guide Chapter Functional SimulationCadence IUS Chapter 4 Functional Simulation Mentor Graphics ModelSimVerilog Mentor Graphics ModelSim VHDLvlib simprim Chapter 4 Functional SimulationChapter Synthesizing a DesignSynplicity Synplify Figure 5-1 Create a New ProjectFigure 5-2 Main Project Window Chapter 5 Synthesizing a DesignFigure 5-4 Files to Add LogiCORE Files Synplicity SynplifyFigure 5-3 Files to Add Virtex Library 7. Navigate to the source directory Figure 5-5, select the cfgtests.v, pcixtop.v, and userapp.v files, and then click Add Figure 5-5 Files to Add User ApplicationFigure 5-6 Source Files in Main Project Window Chapter 5 Synthesizing a DesignFigure 5-8 Options for Implementation Options/Constraints Figure 5-7 Options for Implementation DeviceSynplicity Synplify 10. Click Change Result File to display the EDIF Result File dialog box then move the to following directoryChapter 5 Synthesizing a Design Figure 5-9 Create a New ProjectInstall Path/vhdl/example/synthesis VHDL3. Click OK to exit the dialog and return to the project window Figure Figure 5-10 Main Project WindowFigure 5-11 Files to Add Virtex Library Synplicity SynplifyInstall Path/vhdl/example/source Figure 5-12 Files to Add LogiCORE FilesFigure 5-13 Files to Add User Application Install Path/vhdl/src/xpci8. In the Source Files list, view the list of newly added source files by double-clicking the flowtest/vhdl folder if it is not already open. Drag to reorder the source files in the hierarchical order shown in Figure Figure 5-14 Main Project WindowSynplicity Synplify Chapter 5 Synthesizing a Design Exemplar LeonardoSpectrumFigure 5-15 Options for Implementation Device Xilinx XST Xilinx XSTUG158 March 24 Chapter 5 Synthesizing a DesignPCI-X v5.1 165 Getting Started Guide Chapter Implementing a DesignISE Foundation Chapter 6 Implementing a Design Cadence IUS Timing Simulationcd Install Path/verilog/example/postsim cp ../xilinx/*.v ChapterVHDL Chapter 7 Timing SimulationMentor Graphics ModelSim VerilogMentor Graphics ModelSim Install Path/vhdl/example/postsim

Conventions

Online Document

See “Additional Resources”

Blue text

See “Title Formats” in Chapter

Blue, underlined text