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Xilinx PCI-X v5.1 Additional Documentation, Technical Support, Feedback, Core Interface for PCI-X

Models: PCI-X v5.1

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Chapter 1: Getting Started

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Chapter 1: Getting Started

Step-by-step instructions using supported design tools are provided in this guide to simulate, synthesize, and implement the Userapp example design.

Additional Documentation

For more information about the core interface, see the following documents, provided in the CORE Generator zip file:

•Initiator/Target v5.1 for PCI-X User Guide

•Initiator/Target v5.1 Release Notes

Further information is available in the Mindshare PCI System Architecture text, and the PCI Local Bus Specification, available from the PCI Special Interest Group site.

Technical Support

For technical support, visit www.xilinx.com/support. Questions are routed to a team of engineers with expertise using the Initiator/Target core for PCI-X.

Xilinx provides technical support for use of this product as described in the User and Getting Started Guides for this core. Xilinx cannot guarantee timing, functionality, or support of this product for designs outside of these guidelines.

Feedback

Xilinx welcomes comments and suggestions about the core interface for PCI-X and the documentation supplied with the core.

Core Interface for PCI-X

For comments or suggestions about the core interface for PCI-X, please submit a WebCase from www.xilinx.com/support/clearexpress/websupport.htmt. Be sure to include the following information:

•Product name

•Core version number

•Explanation of your comments

Document

For comments or suggestions about this document, please submit a WebCase from www.xilinx.com/support/clearexpress/websupport.htm. Be sure to include the following information:

•Document title and number

•Page number(s) to which your comments refer

•Explanation of your comments

14	www.xilinx.com	PCI-X v5.1 165 Getting Started Guide
		UG158 March 24, 2008

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Xilinx PCI-X v5.1 manual Additional Documentation, Technical Support, Feedback, Core Interface for PCI-X, Getting Started

Contents

Getting Started Guide UG158 March 24LogiCORE IP Initiator/Target v5.1 for PCI-X PCI-X v5.1 165 Getting Started Guide UG158 March 24 VersionRevision ug000preface.fm to “Guide.” VersionRevision Revision Updated tools for IP0K releaseVersion 10/10/07Chapter 1 Getting Started Table of ContentsPreface About This Guide Chapter 2 Licensing the CoreVerilog VHDL Exemplar LeonardoSpectrum Xilinx XST Chapter 6 Implementing a DesignChapter 7 Timing Simulation ISE FoundationChapter 4 Functional Simulation Chapter 5 Synthesizing a Design Schedule of FiguresChapter 1 Getting Started Chapter 2 Licensing the Core Chapter 6 Implementing a Design Chapter 7 Timing SimulationPCI-X v5.1 165 Getting Started Guide UG158 March 24Preface Guide ContentsAbout This Guide Preface About This Guide ConventionsTypographical ConventionSee “Additional Resources” Online DocumentConventions Blue textUG158 March 24 Preface About This GuidePCI-X v5.1 165 Getting Started Guide System Requirements Getting StartedChapter About the Example DesignFeedback Additional DocumentationTechnical Support Core Interface for PCI-XLicensing Options Licensing the CoreBefore you Begin Full System Hardware EvaluationDirect Download Installing Your License FileFull License Obtaining a Full LicenseTable 3-1 Device and Interface Selection Family Specific ConsiderationsDesign Support Supported DeviceTable 3-1 Device and Interface Selection Chapter 3 Family Specific ConsiderationsWrapper File Supported DeviceSupported Device Design Support Table 3-1 Device and Interface SelectionWrapper File Bus TypeChapter 3 Family Specific Considerations Wrapper FilesConstraints Files Table 3-1 Device and Interface SelectionDevice Initialization Configuration PinsBus Mode Detection Bus Width DetectionDesired System Interface Implementation Bus Clock UsageTable 3-2 Bitstream Requirements BitstreamsElectrical Compliance 3.6 volts, as allowed by the PCI Local Bus SpecificationElectrical Compliance Figure 3-1 PCI/PCI-X Output Driver VCCO GenerationInput Delay Buffers Chapter 3 Family Specific ConsiderationsGenerating Bitstreams Generating BitstreamsUG158 March 24 Chapter 3 Family Specific ConsiderationsPCI-X v5.1 165 Getting Started Guide Chapter Functional SimulationCadence IUS Chapter 4 Functional Simulation Mentor Graphics ModelSimVerilog VHDL Mentor Graphics ModelSimChapter 4 Functional Simulation vlib simprimFigure 5-1 Create a New Project Synthesizing a DesignSynplicity Synplify ChapterChapter 5 Synthesizing a Design Figure 5-2 Main Project WindowFigure 5-4 Files to Add LogiCORE Files Synplicity SynplifyFigure 5-3 Files to Add Virtex Library Chapter 5 Synthesizing a Design Figure 5-5 Files to Add User ApplicationFigure 5-6 Source Files in Main Project Window 7. Navigate to the source directory Figure 5-5, select the cfgtests.v, pcixtop.v, and userapp.v files, and then click Add10. Click Change Result File to display the EDIF Result File dialog box then move the to following directory Figure 5-7 Options for Implementation DeviceSynplicity Synplify Figure 5-8 Options for Implementation Options/ConstraintsVHDL Figure 5-9 Create a New ProjectInstall Path/vhdl/example/synthesis Chapter 5 Synthesizing a DesignSynplicity Synplify Figure 5-10 Main Project WindowFigure 5-11 Files to Add Virtex Library 3. Click OK to exit the dialog and return to the project window FigureInstall Path/vhdl/src/xpci Figure 5-12 Files to Add LogiCORE FilesFigure 5-13 Files to Add User Application Install Path/vhdl/example/source8. In the Source Files list, view the list of newly added source files by double-clicking the flowtest/vhdl folder if it is not already open. Drag to reorder the source files in the hierarchical order shown in Figure Figure 5-14 Main Project WindowSynplicity Synplify Chapter 5 Synthesizing a Design Exemplar LeonardoSpectrumFigure 5-15 Options for Implementation Device Xilinx XST Xilinx XSTUG158 March 24 Chapter 5 Synthesizing a DesignPCI-X v5.1 165 Getting Started Guide Chapter Implementing a DesignISE Foundation Chapter 6 Implementing a Design Chapter Timing Simulationcd Install Path/verilog/example/postsim cp ../xilinx/*.v Cadence IUSVerilog Chapter 7 Timing SimulationMentor Graphics ModelSim VHDLInstall Path/vhdl/example/postsim Mentor Graphics ModelSim