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Xilinx PCI-X v5.1 10 Main Project Window, 11 Files to Add Virtex Library, Synplicity Synplify

Models: PCI-X v5.1

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Synplicity Synplify

3.Click OK to exit the dialog and return to the project window (Figure 5-10).

Figure 5-10:Main Project Window

4.To add source files to the new project, click Add.

The first file (used by any design that instantiates Xilinx primitives) is located in:

<Synplicity Install Path>/lib/xilinx

5.Select the virtex.vhd file (Figure 5-11); then click Add to move the file into the Files To Add list.

Figure 5-11:Files to Add (Virtex Library)

PCI-X v5.1 165 Getting Started Guide

www.xilinx.com

UG158 March 24, 2008

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Xilinx PCI-X v5.1 manual 10 Main Project Window, 11 Files to Add Virtex Library, Synplicity Synplify

Contents

LogiCORE IP Initiator/Target v5.1 for PCI-X UG158 March 24Getting Started Guide Revision VersionPCI-X v5.1 165 Getting Started Guide UG158 March 24 Revision Versionug000preface.fm to “Guide.” Version Updated tools for IP0K releaseRevision 10/10/07Preface About This Guide Table of ContentsChapter 1 Getting Started Chapter 2 Licensing the CoreChapter 7 Timing Simulation Chapter 6 Implementing a DesignVerilog VHDL Exemplar LeonardoSpectrum Xilinx XST ISE FoundationChapter 1 Getting Started Chapter 2 Licensing the Core Schedule of FiguresChapter 4 Functional Simulation Chapter 5 Synthesizing a Design Chapter 6 Implementing a Design Chapter 7 Timing SimulationUG158 March 24 PCI-X v5.1 165 Getting Started GuideAbout This Guide Guide ContentsPreface Typographical ConventionsPreface About This Guide ConventionConventions Online DocumentSee “Additional Resources” Blue textPCI-X v5.1 165 Getting Started Guide Preface About This GuideUG158 March 24 Chapter Getting StartedSystem Requirements About the Example DesignTechnical Support Additional DocumentationFeedback Core Interface for PCI-XBefore you Begin Licensing the CoreLicensing Options Full System Hardware EvaluationFull License Installing Your License FileDirect Download Obtaining a Full LicenseDesign Support Family Specific ConsiderationsTable 3-1 Device and Interface Selection Supported DeviceWrapper File Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Supported DeviceWrapper File Design Support Table 3-1 Device and Interface SelectionSupported Device Bus TypeConstraints Files Wrapper FilesChapter 3 Family Specific Considerations Table 3-1 Device and Interface SelectionBus Mode Detection Configuration PinsDevice Initialization Bus Width DetectionTable 3-2 Bitstream Requirements Bus Clock UsageDesired System Interface Implementation BitstreamsElectrical Compliance 3.6 volts, as allowed by the PCI Local Bus SpecificationElectrical Compliance Figure 3-1 PCI/PCI-X Output Driver VCCO GenerationChapter 3 Family Specific Considerations Input Delay BuffersGenerating Bitstreams Generating BitstreamsPCI-X v5.1 165 Getting Started Guide Chapter 3 Family Specific ConsiderationsUG158 March 24 Cadence IUS Functional SimulationChapter Verilog Mentor Graphics ModelSimChapter 4 Functional Simulation Mentor Graphics ModelSim VHDLvlib simprim Chapter 4 Functional SimulationSynplicity Synplify Synthesizing a DesignFigure 5-1 Create a New Project ChapterFigure 5-2 Main Project Window Chapter 5 Synthesizing a DesignFigure 5-3 Files to Add Virtex Library Synplicity SynplifyFigure 5-4 Files to Add LogiCORE Files Figure 5-6 Source Files in Main Project Window Figure 5-5 Files to Add User ApplicationChapter 5 Synthesizing a Design 7. Navigate to the source directory Figure 5-5, select the cfgtests.v, pcixtop.v, and userapp.v files, and then click AddSynplicity Synplify Figure 5-7 Options for Implementation Device10. Click Change Result File to display the EDIF Result File dialog box then move the to following directory Figure 5-8 Options for Implementation Options/ConstraintsInstall Path/vhdl/example/synthesis Figure 5-9 Create a New ProjectVHDL Chapter 5 Synthesizing a DesignFigure 5-11 Files to Add Virtex Library Figure 5-10 Main Project WindowSynplicity Synplify 3. Click OK to exit the dialog and return to the project window FigureFigure 5-13 Files to Add User Application Figure 5-12 Files to Add LogiCORE FilesInstall Path/vhdl/src/xpci Install Path/vhdl/example/sourceSynplicity Synplify Figure 5-14 Main Project Window8. In the Source Files list, view the list of newly added source files by double-clicking the flowtest/vhdl folder if it is not already open. Drag to reorder the source files in the hierarchical order shown in Figure Figure 5-15 Options for Implementation Device Exemplar LeonardoSpectrumChapter 5 Synthesizing a Design Xilinx XST Xilinx XSTPCI-X v5.1 165 Getting Started Guide Chapter 5 Synthesizing a DesignUG158 March 24 ISE Foundation Implementing a DesignChapter Chapter 6 Implementing a Design cd Install Path/verilog/example/postsim cp ../xilinx/*.v Timing SimulationChapter Cadence IUSMentor Graphics ModelSim Chapter 7 Timing SimulationVerilog VHDLMentor Graphics ModelSim Install Path/vhdl/example/postsim