Xilinx PCI-X v5.1 manual Timing Simulation, Mentor Graphics ModelSim, Verilog, Vhdl, simvision

R

Chapter 7: Timing Simulation

The SimVision browser may be used to view simulation results. SimVision is started with the following command:

simvision

Mentor Graphics ModelSim

Before attempting functional simulation, ensure that the ModelSim environment is properly configured for use.

Verilog

1.Navigate to the timing simulation directory and copy the back annotated timing models from the implementation directory:

cd <Install Path>/verilog/example/post_sim cp ../xilinx/*.v ./

cp ../xilinx/*.sdf ./

2.Edit the test_tb.f file. This file lists command line arguments for ModelSim, and is shown below:

../source/stimulus.v

../source/test_tb.v

../source/busrec.v

./pcix_top_s_routed.v +libext+.vmd+.v

-y <Xilinx Install Path>/verilog/src/simprims

Modify the library search path by changing <Xilinx Install Path> to match the Xilinx installation directory. Save the file.

3.Invoke ModelSim, and ensure that the current directory is set to:

<Install Path>/verilog/example/post_sim

4.To run the simulation: do modelsim.do

This compiles all modules, loads them into the simulator, displays the waveform viewer, and runs the simulation.

VHDL

1.Navigate to the timing simulation directory and copy the back annotated timing models from the implementation directory:

cd <Install Path>/vhdl/example/post_sim cp ../xilinx/*.vhd ./

cp ../xilinx/*.sdf ./

2.View the test.files file. This file lists the individual source files required, and is shown below:

./pcix_top_s_routed.vhd

../source/busrec.vhd

../source/stimulus.vhd

../source/test_tb.vhd

46	www.xilinx.com	PCI-X v5.1 165 Getting Started Guide
		UG158 March 24, 2008