Generating Bitstreams | Xilinx PCI-X v5.1 manual

Generating Bitstreams

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Generating Bitstreams

The bitstream generation program, bitgen, may issue DRC warnings when generating bitstreams for PCI-X designs. The number of these warnings varies depending on the configuration options used for the PCI-X core. Typically, these warnings are related to nets with no loads generated during trimming by the map program. Some of these nets are intentionally preserved by statements in the user constraints file.

Please be aware that the bitgen options provided with the example design are only for reference. The actual options used will depend on the desired FPGA configuration method and clock rate of your complete design, as implemented on a board. Please carefully consider the following configuration time requirements when selecting a configuration method and clock rate.

1.Any designs that do not automatically sense both the bus width and bus mode must be configured within (100 ms + 225 bus clocks) after the bus power rails become valid.

2.Any designs that must sense either the bus width or the bus mode must be configured within 100 ms after the bus power rails become valid.

3.Cardbus designs must be configured as quickly as possible after the bus power rails become valid.

PCI-X v5.1 165 Getting Started Guide

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UG158 March 24, 2008

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Xilinx PCI-X v5.1 manual Generating Bitstreams

Contents

UG158 March 24 LogiCORE IP Initiator/Target v5.1 for PCI-X Version Revision PCI-X v5.1 165 Getting Started Guide UG158 March 24 Ug000preface.fm to Guide Version Revision Table of Contents Implementing a Design 8Options for Implementation Options/Constraints Schedule of Figures PCI-X v5.1 165 Getting Started Guide About This Guide Guide Contents Typographical ConventionsPreface About This Guide Convention Meaning or Use Example Conventions Online Document Preface About This Guide System Requirements Getting StartedAbout the Example Design Technical Support Additional DocumentationFeedback Core Interface for PCI-X Before you Begin Licensing the CoreLicensing Options Full System Hardware Evaluation Full License Installing Your License FileDirect Download Licensing the Core Design Support Family Specific Considerations Simulation Virtex-4 Devices Wrapper Files Bus Mode Detection Configuration PinsDevice Initialization Bus Width Detection Family Specific Considerations Bus Clock Usage Electrical Compliance Electrical Compliance Input Delay Buffers Generating Bitstreams Generating Bitstreams Family Specific Considerations Cadence IUS Functional Simulation Verilog Mentor Graphics ModelSimFunctional Simulation Mentor Graphics ModelSim Install Path/verilog/example/funcsim To run the simulation, type the following do modelsim.do Synplicity Synplify Synthesizing a Design 2Main Project Window Synthesizing a Design 3Files to Add Virtex Library Synplicity Synplify 5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window 15Options for Implementation Device Exemplar LeonardoSpectrum Xilinx XST Xilinx XST Synthesizing a Design ISE Foundation Implementing a Design Implementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim