Xilinx PCI-X v5.1 manual Implementing a Design, ISE Foundation, Chapter

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Implementing a Design

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Chapter 6

Implementing a Design

This chapter describes the use of supported FPGA implementation tools using the Userapp example design. If you are using a design with reference clocks, substitute pcix_top with pcix_top_r and test_tb with test_tb_r.

Supported FPGA implementation tools are included with the ISE Foundation v10.1 software.

ISE Foundation

Before implementing a design, ensure that the Xilinx environment is properly configured and that the design has been successfully synthesized.

1.Navigate to the implementation directory: cd <Install Path>/hdl/example/xilinx

This directory contains the run_xil_n, run_xil_s, and run_xil_x scripts. These call the appropriate tools to place and route the example design in one of three possible incarnations: PCI only, Dual Mode, and PCI-X only. Use the script that corresponds to the core configuration you have selected. For the default example design, the Dual Mode script should be used.

2.Inspect the appropriate script file and note the following:

The ngdbuild command lists both../../src/xpci and../synthesis as search directories. The xpci directory contains a netlist of the core interface, and the synthesis directory must contain the EDIF netlist generated during design synthesis.

The ngdbuild command also reads a user constraints file that corresponds to a desired target device and a particular version of the core interface.

To target a different device or to use a different version of the core interface, the constraints file must be changed to match the device and interface selection. The available selections are listed in the Chapter 3, “Family Specific Considerations.”

The user constraints files provided with the core interface contain constraints that guarantee pinout and timing specifications. These constraints must be used during processing.

Any additional constraints that pertain to the user application must be placed in this file. Before making additions to the user constraints file, back up the original so that it may be restored if necessary.

The map command requires no special arguments, but uses an input/output register packing option.

The PAR effort levels and delay cleanup iterations may be adjusted if necessary.

PCI-X v5.1 165 Getting Started Guide

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UG158 March 24, 2008

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Xilinx PCI-X v5.1 manual Implementing a Design, ISE Foundation, Chapter