Schedule of Figures | Xilinx PCI-X v5.1 specification

Schedule of Figures

Chapter 1: Getting Started

Chapter 2: Licensing the Core

Chapter 3: Family Specific Considerations

Figure 3-1:PCI/PCI-X Output Driver VCCO Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Chapter 4: Functional Simulation

Chapter 5: Synthesizing a Design

Figure 5-1:Create a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 5-2:Main Project Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 5-3:Files to Add (Virtex Library) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 5-4:Files to Add (LogiCORE Files). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 5-5:Files to Add (User Application) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 5-6:Source Files in Main Project Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 5-7:Options for Implementation: Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 5-8:Options for Implementation: Options/Constraints. . . . . . . . . . . . . . . . . . . . . 35

Figure 5-9:Create a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 5-10:Main Project Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 5-11:Files to Add (Virtex Library) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 5-12:Files to Add (LogiCORE Files). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 5-13:Files to Add (User Application) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 5-14:Main Project Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 5-15:Options for Implementation: Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Chapter 6: Implementing a Design

Chapter 7: Timing Simulation

www.xilinx.com	PCI-X v5.1 165 Getting Started Guide
	UG158 March 24, 2008

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Xilinx PCI-X v5.1 manual Schedule of Figures, 8Options for Implementation Options/Constraints

Contents

UG158 March 24 LogiCORE IP Initiator/Target v5.1 for PCI-X Version Revision PCI-X v5.1 165 Getting Started Guide UG158 March 24 Ug000preface.fm to Guide Version Revision Table of Contents Implementing a Design 8Options for Implementation Options/Constraints Schedule of Figures PCI-X v5.1 165 Getting Started Guide About This Guide Guide Contents Convention Meaning or Use Example ConventionsTypographical Preface About This Guide Conventions Online Document Preface About This Guide System Requirements Getting StartedAbout the Example Design Core Interface for PCI-X Additional DocumentationTechnical Support Feedback Full System Hardware Evaluation Licensing the CoreBefore you Begin Licensing Options Licensing the Core Installing Your License FileFull License Direct Download Design Support Family Specific Considerations Simulation Virtex-4 Devices Wrapper Files Bus Width Detection Configuration PinsBus Mode Detection Device Initialization Family Specific Considerations Bus Clock Usage Electrical Compliance Electrical Compliance Input Delay Buffers Generating Bitstreams Generating Bitstreams Family Specific Considerations Cadence IUS Functional Simulation Verilog Mentor Graphics ModelSimFunctional Simulation Mentor Graphics ModelSim Install Path/verilog/example/funcsim To run the simulation, type the following do modelsim.do Synplicity Synplify Synthesizing a Design 2Main Project Window Synthesizing a Design 3Files to Add Virtex Library Synplicity Synplify 5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window 15Options for Implementation Device Exemplar LeonardoSpectrum Xilinx XST Xilinx XST Synthesizing a Design ISE Foundation Implementing a Design Implementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim