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PCI-X v5.1 manual UG158 March 24, LogiCORE IP Initiator/Target v5.1 for PCI-X
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Updated tools for IP0K release
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LogiCORE™ IP Initiator/Target v5.1 for
PCI-X™
Getting Started Guide
UG158 March 24, 2008
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Contents
LogiCORE IP Initiator/Target v5.1 for PCI-X
UG158 March 24
Getting Started Guide
Revision
Version
PCI-X v5.1 165 Getting Started Guide UG158 March 24
Revision
Version
ug000preface.fm to “Guide.”
Version
Updated tools for IP0K release
Revision
10/10/07
Preface About This Guide
Table of Contents
Chapter 1 Getting Started
Chapter 2 Licensing the Core
Chapter 7 Timing Simulation
Chapter 6 Implementing a Design
Verilog VHDL Exemplar LeonardoSpectrum Xilinx XST
ISE Foundation
Chapter 1 Getting Started Chapter 2 Licensing the Core
Schedule of Figures
Chapter 4 Functional Simulation Chapter 5 Synthesizing a Design
Chapter 6 Implementing a Design Chapter 7 Timing Simulation
UG158 March 24
PCI-X v5.1 165 Getting Started Guide
About This Guide
Guide Contents
Preface
Typographical
Conventions
Preface About This Guide
Convention
Conventions
Online Document
See “Additional Resources”
Blue text
PCI-X v5.1 165 Getting Started Guide
Preface About This Guide
UG158 March 24
Chapter
Getting Started
System Requirements
About the Example Design
Technical Support
Additional Documentation
Feedback
Core Interface for PCI-X
Before you Begin
Licensing the Core
Licensing Options
Full System Hardware Evaluation
Full License
Installing Your License File
Direct Download
Obtaining a Full License
Design Support
Family Specific Considerations
Table 3-1 Device and Interface Selection
Supported Device
Wrapper File
Chapter 3 Family Specific Considerations
Table 3-1 Device and Interface Selection
Supported Device
Wrapper File
Design Support Table 3-1 Device and Interface Selection
Supported Device
Bus Type
Constraints Files
Wrapper Files
Chapter 3 Family Specific Considerations
Table 3-1 Device and Interface Selection
Bus Mode Detection
Configuration Pins
Device Initialization
Bus Width Detection
Table 3-2 Bitstream Requirements
Bus Clock Usage
Desired System Interface Implementation
Bitstreams
Electrical Compliance
3.6 volts, as allowed by the PCI Local Bus Specification
Electrical Compliance
Figure 3-1 PCI/PCI-X Output Driver VCCO Generation
Chapter 3 Family Specific Considerations
Input Delay Buffers
Generating Bitstreams
Generating Bitstreams
PCI-X v5.1 165 Getting Started Guide
Chapter 3 Family Specific Considerations
UG158 March 24
Cadence IUS
Functional Simulation
Chapter
Verilog
Mentor Graphics ModelSim
Chapter 4 Functional Simulation
Mentor Graphics ModelSim
VHDL
vlib simprim
Chapter 4 Functional Simulation
Synplicity Synplify
Synthesizing a Design
Figure 5-1 Create a New Project
Chapter
Figure 5-2 Main Project Window
Chapter 5 Synthesizing a Design
Figure 5-3 Files to Add Virtex Library
Synplicity Synplify
Figure 5-4 Files to Add LogiCORE Files
Figure 5-6 Source Files in Main Project Window
Figure 5-5 Files to Add User Application
Chapter 5 Synthesizing a Design
7. Navigate to the source directory Figure 5-5, select the cfgtests.v, pcixtop.v, and userapp.v files, and then click Add
Synplicity Synplify
Figure 5-7 Options for Implementation Device
10. Click Change Result File to display the EDIF Result File dialog box then move the to following directory
Figure 5-8 Options for Implementation Options/Constraints
Install Path/vhdl/example/synthesis
Figure 5-9 Create a New Project
VHDL
Chapter 5 Synthesizing a Design
Figure 5-11 Files to Add Virtex Library
Figure 5-10 Main Project Window
Synplicity Synplify
3. Click OK to exit the dialog and return to the project window Figure
Figure 5-13 Files to Add User Application
Figure 5-12 Files to Add LogiCORE Files
Install Path/vhdl/src/xpci
Install Path/vhdl/example/source
Synplicity Synplify
Figure 5-14 Main Project Window
8. In the Source Files list, view the list of newly added source files by double-clicking the flowtest/vhdl folder if it is not already open. Drag to reorder the source files in the hierarchical order shown in Figure
Figure 5-15 Options for Implementation Device
Exemplar LeonardoSpectrum
Chapter 5 Synthesizing a Design
Xilinx XST
Xilinx XST
PCI-X v5.1 165 Getting Started Guide
Chapter 5 Synthesizing a Design
UG158 March 24
ISE Foundation
Implementing a Design
Chapter
Chapter 6 Implementing a Design
cd Install Path/verilog/example/postsim cp ../xilinx/*.v
Timing Simulation
Chapter
Cadence IUS
Mentor Graphics ModelSim
Chapter 7 Timing Simulation
Verilog
VHDL
Mentor Graphics ModelSim
Install Path/vhdl/example/postsim
