Virtex-4 Devices | Xilinx PCI-X v5.1 guide

Design Support

Table 3-1:Device and Interface Selection

				Wrapper File
Supported Device		Bus Type		Simulation		Constraints File
				Model
2VP40-FF1152-6C/I		66 MHz PCI-X		pcix_lc_64x		2vp40ff1152_64x.ucf
		3.3V 64-bit		pcix_core
2VP40-FF1152-6C/I		100 MHz PCI-X		pcix_lc_64xf		2vp40ff1152_64xf.ucf
		3.3V 64-bit		pcix_fast
2VP40-FF1152-6C/I		133 MHz PCI-X		pcix_lc_64xf		2vp40ff1152_64xf.ucf
		3.3V 64-bit		pcix_fast
2VP40-FF1152-6C/I		33 MHz PCI		pcix_lc_64s		2vp40ff1152_64s.ucf
		66 MHz PCI-X		pcix_core
		3.3V 64-bit
2VP50-FF1152-6C/I		33 MHz PCI		pcix_lc_64n		2vp50ff1152_64n.ucf
		3.3V 64-bit		pcix_core
2VP50-FF1152-6C/I		66 MHz PCI-X		pcix_lc_64x		2vp50ff1152_64x.ucf
		3.3V 64-bit		pcix_core
2VP50-FF1152-6C/I		100 MHz PCI-X		pcix_lc_64xf		2vp50ff1152_64xf.ucf
		3.3V 64-bit		pcix_fast
2VP50-FF1152-6C/I		133 MHz PCI-X		pcix_lc_64xf		2vp50ff1152_64xf.ucf
		3.3V 64-bit		pcix_fast
2VP50-FF1152-6C/I		33 MHz PCI		pcix_lc_64s		2vp50ff1152_64s.ucf
		66 MHz PCI-X		pcix_core
		3.3V 64-bit

		Virtex-4 Devices
4VFX20-FF672-10C/I		33 MHz PCI		pcix_lc_64.ng		4vfx20ff672_64ng.ucf
4VFX20-FF672-10C/I		33 MHz PCI		pcix_lc_64.ng		4vfx20ff672_64ng.ucf
		3.3V 64-bit		pcix_core
4VFX20-FF672-10C/I		66 MHz PCI-X		pcix_lc_64x		4vfx20ff672_64x.ucf
		3.3V 64-bit		pcix_core
4VFX20-FF672-10C/I		100 MHz PCI-X		pcix_lc_64x		4vfx20ff672_64xf.ucf
		3.3V 64-bit		pcix_core
4VFX20-FF672-10C/I		133 MHz PCI-X		pcix_lc_64x		4vfx20ff672_64xf.ucf
		3.3V 64-bit		pcix_core
4VLX25-FF668-10C/I		33 MHz PCI		pcix_lc_64.ng		4vlx25ff668_64ng.ucf
		3.3V 64-bit		pcix_core
4VLX25-FF668-10C/I		66 MHz PCI-X		pcix_lc_64x		4vlx25ff668_64x.ucf
		3.3V 64-bit		pcix_core

R

PCI-X v5.1 165 Getting Started Guide

www.xilinx.com

19

UG158 March 24, 2008

Image 19

Xilinx PCI-X v5.1 manual Virtex-4 Devices

Contents

UG158 March 24 LogiCORE IP Initiator/Target v5.1 for PCI-X Version Revision PCI-X v5.1 165 Getting Started Guide UG158 March 24 Ug000preface.fm to Guide Version Revision Table of Contents Implementing a Design 8Options for Implementation Options/Constraints Schedule of Figures PCI-X v5.1 165 Getting Started Guide About This Guide Guide Contents Convention Meaning or Use Example ConventionsTypographical Preface About This Guide Conventions Online Document Preface About This Guide System Requirements Getting StartedAbout the Example Design Core Interface for PCI-X Additional DocumentationTechnical Support Feedback Full System Hardware Evaluation Licensing the CoreBefore you Begin Licensing Options Licensing the Core Installing Your License FileFull License Direct Download Design Support Family Specific Considerations Simulation Virtex-4 Devices Wrapper Files Bus Width Detection Configuration PinsBus Mode Detection Device Initialization Family Specific Considerations Bus Clock Usage Electrical Compliance Electrical Compliance Input Delay Buffers Generating Bitstreams Generating Bitstreams Family Specific Considerations Cadence IUS Functional Simulation Verilog Mentor Graphics ModelSimFunctional Simulation Mentor Graphics ModelSim Install Path/verilog/example/funcsim To run the simulation, type the following do modelsim.do Synplicity Synplify Synthesizing a Design 2Main Project Window Synthesizing a Design 3Files to Add Virtex Library Synplicity Synplify 5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window 15Options for Implementation Device Exemplar LeonardoSpectrum Xilinx XST Xilinx XST Synthesizing a Design ISE Foundation Implementing a Design Implementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim