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Xilinx PCI-X v5.1 manual Design Support -1 Device and Interface Selection, Wrapper File, Bus Type

Models: PCI-X v5.1

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Design Support

Design Support

Table 3-1:Device and Interface Selection

				Wrapper File
Supported Device		Bus Type		Simulation		Constraints File
				Model
2VP40-FF1152-6C/I		66 MHz PCI-X		pcix_lc_64x		2vp40ff1152_64x.ucf
		3.3V 64-bit		pcix_core
2VP40-FF1152-6C/I		100 MHz PCI-X		pcix_lc_64xf		2vp40ff1152_64xf.ucf
		3.3V 64-bit		pcix_fast
2VP40-FF1152-6C/I		133 MHz PCI-X		pcix_lc_64xf		2vp40ff1152_64xf.ucf
		3.3V 64-bit		pcix_fast
2VP40-FF1152-6C/I		33 MHz PCI		pcix_lc_64s		2vp40ff1152_64s.ucf
		66 MHz PCI-X		pcix_core
		3.3V 64-bit
2VP50-FF1152-6C/I		33 MHz PCI		pcix_lc_64n		2vp50ff1152_64n.ucf
		3.3V 64-bit		pcix_core
2VP50-FF1152-6C/I		66 MHz PCI-X		pcix_lc_64x		2vp50ff1152_64x.ucf
		3.3V 64-bit		pcix_core
2VP50-FF1152-6C/I		100 MHz PCI-X		pcix_lc_64xf		2vp50ff1152_64xf.ucf
		3.3V 64-bit		pcix_fast
2VP50-FF1152-6C/I		133 MHz PCI-X		pcix_lc_64xf		2vp50ff1152_64xf.ucf
		3.3V 64-bit		pcix_fast
2VP50-FF1152-6C/I		33 MHz PCI		pcix_lc_64s		2vp50ff1152_64s.ucf
		66 MHz PCI-X		pcix_core
		3.3V 64-bit

		Virtex-4 Devices
4VFX20-FF672-10C/I		33 MHz PCI		pcix_lc_64.ng		4vfx20ff672_64ng.ucf
4VFX20-FF672-10C/I		33 MHz PCI		pcix_lc_64.ng		4vfx20ff672_64ng.ucf
		3.3V 64-bit		pcix_core
4VFX20-FF672-10C/I		66 MHz PCI-X		pcix_lc_64x		4vfx20ff672_64x.ucf
		3.3V 64-bit		pcix_core
4VFX20-FF672-10C/I		100 MHz PCI-X		pcix_lc_64x		4vfx20ff672_64xf.ucf
		3.3V 64-bit		pcix_core
4VFX20-FF672-10C/I		133 MHz PCI-X		pcix_lc_64x		4vfx20ff672_64xf.ucf
		3.3V 64-bit		pcix_core
4VLX25-FF668-10C/I		33 MHz PCI		pcix_lc_64.ng		4vlx25ff668_64ng.ucf
		3.3V 64-bit		pcix_core
4VLX25-FF668-10C/I		66 MHz PCI-X		pcix_lc_64x		4vlx25ff668_64x.ucf
		3.3V 64-bit		pcix_core

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PCI-X v5.1 165 Getting Started Guide

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UG158 March 24, 2008

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Xilinx PCI-X v5.1 manual Design Support -1 Device and Interface Selection, Wrapper File, Supported Device, Bus Type

Contents

LogiCORE IP Initiator/Target v5.1 for PCI-X UG158 March 24Getting Started Guide Revision VersionPCI-X v5.1 165 Getting Started Guide UG158 March 24 Revision Versionug000preface.fm to “Guide.” 10/10/07 Updated tools for IP0K releaseVersion RevisionChapter 2 Licensing the Core Table of ContentsPreface About This Guide Chapter 1 Getting StartedISE Foundation Chapter 6 Implementing a DesignChapter 7 Timing Simulation Verilog VHDL Exemplar LeonardoSpectrum Xilinx XSTChapter 6 Implementing a Design Chapter 7 Timing Simulation Schedule of FiguresChapter 1 Getting Started Chapter 2 Licensing the Core Chapter 4 Functional Simulation Chapter 5 Synthesizing a DesignUG158 March 24 PCI-X v5.1 165 Getting Started GuideAbout This Guide Guide ContentsPreface Convention ConventionsTypographical Preface About This GuideBlue text Online DocumentConventions See “Additional Resources”PCI-X v5.1 165 Getting Started Guide Preface About This GuideUG158 March 24 About the Example Design Getting StartedChapter System RequirementsCore Interface for PCI-X Additional DocumentationTechnical Support FeedbackFull System Hardware Evaluation Licensing the CoreBefore you Begin Licensing OptionsObtaining a Full License Installing Your License FileFull License Direct DownloadSupported Device Family Specific ConsiderationsDesign Support Table 3-1 Device and Interface SelectionSupported Device Chapter 3 Family Specific ConsiderationsWrapper File Table 3-1 Device and Interface SelectionBus Type Design Support Table 3-1 Device and Interface SelectionWrapper File Supported DeviceTable 3-1 Device and Interface Selection Wrapper FilesConstraints Files Chapter 3 Family Specific ConsiderationsBus Width Detection Configuration PinsBus Mode Detection Device InitializationBitstreams Bus Clock UsageTable 3-2 Bitstream Requirements Desired System Interface ImplementationFigure 3-1 PCI/PCI-X Output Driver VCCO Generation 3.6 volts, as allowed by the PCI Local Bus SpecificationElectrical Compliance Electrical ComplianceChapter 3 Family Specific Considerations Input Delay BuffersGenerating Bitstreams Generating BitstreamsPCI-X v5.1 165 Getting Started Guide Chapter 3 Family Specific ConsiderationsUG158 March 24 Cadence IUS Functional SimulationChapter Verilog Mentor Graphics ModelSimChapter 4 Functional Simulation Mentor Graphics ModelSim VHDLvlib simprim Chapter 4 Functional SimulationChapter Synthesizing a DesignSynplicity Synplify Figure 5-1 Create a New ProjectFigure 5-2 Main Project Window Chapter 5 Synthesizing a DesignFigure 5-3 Files to Add Virtex Library Synplicity SynplifyFigure 5-4 Files to Add LogiCORE Files 7. Navigate to the source directory Figure 5-5, select the cfgtests.v, pcixtop.v, and userapp.v files, and then click Add Figure 5-5 Files to Add User ApplicationFigure 5-6 Source Files in Main Project Window Chapter 5 Synthesizing a DesignFigure 5-8 Options for Implementation Options/Constraints Figure 5-7 Options for Implementation DeviceSynplicity Synplify 10. Click Change Result File to display the EDIF Result File dialog box then move the to following directoryChapter 5 Synthesizing a Design Figure 5-9 Create a New ProjectInstall Path/vhdl/example/synthesis VHDL3. Click OK to exit the dialog and return to the project window Figure Figure 5-10 Main Project WindowFigure 5-11 Files to Add Virtex Library Synplicity SynplifyInstall Path/vhdl/example/source Figure 5-12 Files to Add LogiCORE FilesFigure 5-13 Files to Add User Application Install Path/vhdl/src/xpciSynplicity Synplify Figure 5-14 Main Project Window8. In the Source Files list, view the list of newly added source files by double-clicking the flowtest/vhdl folder if it is not already open. Drag to reorder the source files in the hierarchical order shown in Figure Figure 5-15 Options for Implementation Device Exemplar LeonardoSpectrumChapter 5 Synthesizing a Design Xilinx XST Xilinx XSTPCI-X v5.1 165 Getting Started Guide Chapter 5 Synthesizing a DesignUG158 March 24 ISE Foundation Implementing a DesignChapter Chapter 6 Implementing a Design Cadence IUS Timing Simulationcd Install Path/verilog/example/postsim cp ../xilinx/*.v ChapterVHDL Chapter 7 Timing SimulationMentor Graphics ModelSim VerilogMentor Graphics ModelSim Install Path/vhdl/example/postsim