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Xilinx PCI-X v5.1 manual 14 Main Project Window, Synplicity Synplify

Models: PCI-X v5.1

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Synplicity Synplify

8.In the Source Files list, view the list of newly added source files by double-clicking the flowtest/vhdl folder (if it is not already open). Drag to reorder the source files in the hierarchical order shown in Figure 5-14.

Figure 5-14:Main Project Window

9.Click Change Result File to display the EDIF Result File dialog box; then move the to following directory:

<Install Path>/vhdl/example/synthesis

10.Name the file pcix_top.edf and click OK to set the name of the result file and return to the main project window.

Note: In practice, the directory for the EDIF result file does not need to be changed. However, the sample processing scripts included with the example design assume that the output EDIF files will be located in the synthesis directory.

PCI-X v5.1 165 Getting Started Guide

www.xilinx.com

UG158 March 24, 2008

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Xilinx PCI-X v5.1 manual 14 Main Project Window, Synplicity Synplify

Contents

UG158 March 24 LogiCORE IP Initiator/Target v5.1 for PCI-XGetting Started Guide Version RevisionPCI-X v5.1 165 Getting Started Guide UG158 March 24 Version Revisionug000preface.fm to “Guide.” 10/10/07 Updated tools for IP0K releaseVersion RevisionChapter 2 Licensing the Core Table of ContentsPreface About This Guide Chapter 1 Getting StartedISE Foundation Chapter 6 Implementing a DesignChapter 7 Timing Simulation Verilog VHDL Exemplar LeonardoSpectrum Xilinx XSTChapter 6 Implementing a Design Chapter 7 Timing Simulation Schedule of FiguresChapter 1 Getting Started Chapter 2 Licensing the Core Chapter 4 Functional Simulation Chapter 5 Synthesizing a DesignUG158 March 24 PCI-X v5.1 165 Getting Started GuideGuide Contents About This GuidePreface Convention ConventionsTypographical Preface About This GuideBlue text Online DocumentConventions See “Additional Resources”Preface About This Guide PCI-X v5.1 165 Getting Started GuideUG158 March 24 About the Example Design Getting StartedChapter System RequirementsCore Interface for PCI-X Additional DocumentationTechnical Support FeedbackFull System Hardware Evaluation Licensing the CoreBefore you Begin Licensing OptionsObtaining a Full License Installing Your License FileFull License Direct DownloadSupported Device Family Specific ConsiderationsDesign Support Table 3-1 Device and Interface SelectionSupported Device Chapter 3 Family Specific ConsiderationsWrapper File Table 3-1 Device and Interface SelectionBus Type Design Support Table 3-1 Device and Interface SelectionWrapper File Supported DeviceTable 3-1 Device and Interface Selection Wrapper FilesConstraints Files Chapter 3 Family Specific ConsiderationsBus Width Detection Configuration PinsBus Mode Detection Device InitializationBitstreams Bus Clock UsageTable 3-2 Bitstream Requirements Desired System Interface ImplementationFigure 3-1 PCI/PCI-X Output Driver VCCO Generation 3.6 volts, as allowed by the PCI Local Bus SpecificationElectrical Compliance Electrical ComplianceChapter 3 Family Specific Considerations Input Delay BuffersGenerating Bitstreams Generating BitstreamsChapter 3 Family Specific Considerations PCI-X v5.1 165 Getting Started GuideUG158 March 24 Functional Simulation Cadence IUSChapter Mentor Graphics ModelSim VerilogChapter 4 Functional Simulation Mentor Graphics ModelSim VHDLvlib simprim Chapter 4 Functional SimulationChapter Synthesizing a DesignSynplicity Synplify Figure 5-1 Create a New ProjectFigure 5-2 Main Project Window Chapter 5 Synthesizing a DesignSynplicity Synplify Figure 5-3 Files to Add Virtex LibraryFigure 5-4 Files to Add LogiCORE Files 7. Navigate to the source directory Figure 5-5, select the cfgtests.v, pcixtop.v, and userapp.v files, and then click Add Figure 5-5 Files to Add User ApplicationFigure 5-6 Source Files in Main Project Window Chapter 5 Synthesizing a DesignFigure 5-8 Options for Implementation Options/Constraints Figure 5-7 Options for Implementation DeviceSynplicity Synplify 10. Click Change Result File to display the EDIF Result File dialog box then move the to following directoryChapter 5 Synthesizing a Design Figure 5-9 Create a New ProjectInstall Path/vhdl/example/synthesis VHDL3. Click OK to exit the dialog and return to the project window Figure Figure 5-10 Main Project WindowFigure 5-11 Files to Add Virtex Library Synplicity SynplifyInstall Path/vhdl/example/source Figure 5-12 Files to Add LogiCORE FilesFigure 5-13 Files to Add User Application Install Path/vhdl/src/xpciFigure 5-14 Main Project Window Synplicity Synplify8. In the Source Files list, view the list of newly added source files by double-clicking the flowtest/vhdl folder if it is not already open. Drag to reorder the source files in the hierarchical order shown in Figure Exemplar LeonardoSpectrum Figure 5-15 Options for Implementation DeviceChapter 5 Synthesizing a Design Xilinx XST Xilinx XSTChapter 5 Synthesizing a Design PCI-X v5.1 165 Getting Started GuideUG158 March 24 Implementing a Design ISE FoundationChapter Chapter 6 Implementing a Design Cadence IUS Timing Simulationcd Install Path/verilog/example/postsim cp ../xilinx/*.v ChapterVHDL Chapter 7 Timing SimulationMentor Graphics ModelSim VerilogMentor Graphics ModelSim Install Path/vhdl/example/postsim