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Chapter 4
Functional Simulation
This chapter describes how to simulate the Userapp example design using the supported functional simulation tools. If you are using a design with reference clocks, substitute pcix_top with pcix_top_r and test_tb with test_tb_r.
Supported functional simulation tools include
•Cadence IUS v6.1
•Mentor Graphics ModelSim v6.3c
Cadence IUS
Before attempting functional simulation, ensure that the IUS environment is properly configured.
1.Navigate to the functional simulation directory:
cd <Install Path>/verilog/example/func_sim
2.Edit the test_tb.f file. This file lists command line arguments for IUS, as shown below:
../source/glbl.v
../source/cfg_test_s.v
../source/stimulus.v
../source/test_tb.v
../source/busrec.v
../source/pcix_top.v
../source/userapp.v
../../src/xpci/pcix_lc.v
../../src/xpci/pcix_core.v +libext+.vmd+.v
3.Modify the library search path by changing <Xilinx Install Path> to match the Xilinx installation directory. If you have changed the wrapper file, be sure you are using the correct simulation model.
4.Save the file.
Most of the files listed are related to the example design and its test bench. For other test benches, the following subset must be used for proper simulation of the core interface:
../source/glbl.v
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UG158 March 24, 2008
