Implementing a Design | Xilinx PCI-X v5.1 instruction

Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Exemplar LeonardoSpectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Xilinx XST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Chapter 6: Implementing a Design

ISE Foundation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Chapter 7: Timing Simulation

Cadence IUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Mentor Graphics ModelSim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

PCI-X v5.1 165 Getting Started Guide

www.xilinx.com

UG158 March 24, 2008

Image 6

Xilinx PCI-X v5.1 manual Implementing a Design

Contents

LogiCORE IP Initiator/Target v5.1 for PCI-X UG158 March 24 PCI-X v5.1 165 Getting Started Guide UG158 March 24 Version Revision Ug000preface.fm to Guide Version Revision Table of Contents Implementing a Design Schedule of Figures 8Options for Implementation Options/Constraints PCI-X v5.1 165 Getting Started Guide Guide Contents About This Guide Preface About This Guide ConventionsTypographical Convention Meaning or Use Example Online Document Conventions Preface About This Guide Getting Started System RequirementsAbout the Example Design Feedback Additional DocumentationTechnical Support Core Interface for PCI-X Licensing Options Licensing the CoreBefore you Begin Full System Hardware Evaluation Direct Download Installing Your License FileFull License Licensing the Core Family Specific Considerations Design Support Simulation Virtex-4 Devices Wrapper Files Device Initialization Configuration PinsBus Mode Detection Bus Width Detection Bus Clock Usage Family Specific Considerations Electrical Compliance Electrical Compliance Input Delay Buffers Generating Bitstreams Generating Bitstreams Family Specific Considerations Functional Simulation Cadence IUS Mentor Graphics ModelSim VerilogFunctional Simulation Install Path/verilog/example/funcsim Mentor Graphics ModelSim To run the simulation, type the following do modelsim.do Synthesizing a Design Synplicity Synplify Synthesizing a Design 2Main Project Window Synplicity Synplify 3Files to Add Virtex Library 5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window Exemplar LeonardoSpectrum 15Options for Implementation Device Xilinx XST Xilinx XST Synthesizing a Design Implementing a Design ISE Foundation Implementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim