PCI-X v5.1 165 Getting Started Guide | Xilinx specs

PCI-X v5.1 165 Getting Started Guide

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UG158 March 24, 2008

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Xilinx manual PCI-X v5.1 165 Getting Started Guide

Contents

LogiCORE IP Initiator/Target v5.1 for PCI-X UG158 March 24 PCI-X v5.1 165 Getting Started Guide UG158 March 24 Version Revision Ug000preface.fm to Guide Version Revision Table of Contents Implementing a Design Schedule of Figures 8Options for Implementation Options/Constraints PCI-X v5.1 165 Getting Started Guide Guide Contents About This Guide Conventions TypographicalPreface About This Guide Convention Meaning or Use Example Online Document Conventions Preface About This Guide About the Example Design Getting StartedSystem Requirements Additional Documentation Technical SupportFeedback Core Interface for PCI-X Licensing the Core Before you BeginLicensing Options Full System Hardware Evaluation Installing Your License File Full LicenseDirect Download Licensing the Core Family Specific Considerations Design Support Simulation Virtex-4 Devices Wrapper Files Configuration Pins Bus Mode DetectionDevice Initialization Bus Width Detection Bus Clock Usage Family Specific Considerations Electrical Compliance Electrical Compliance Input Delay Buffers Generating Bitstreams Generating Bitstreams Family Specific Considerations Functional Simulation Cadence IUS Functional Simulation Mentor Graphics ModelSimVerilog Install Path/verilog/example/funcsim Mentor Graphics ModelSim To run the simulation, type the following do modelsim.do Synthesizing a Design Synplicity Synplify Synthesizing a Design 2Main Project Window Synplicity Synplify 3Files to Add Virtex Library 5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window Exemplar LeonardoSpectrum 15Options for Implementation Device Xilinx XST Xilinx XST Synthesizing a Design Implementing a Design ISE Foundation Implementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim