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manual PCI-X v5.1 165 Getting Started Guide, UG158 March 24
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Specifications
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Input Delay Buffers
Updated tools for IP0K release
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PCI-X
v5.1 165 Getting Started Guide
www.xilinx.com
UG158 March 24, 2008
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Contents
Getting Started Guide
UG158 March 24
LogiCORE IP Initiator/Target v5.1 for PCI-X
PCI-X v5.1 165 Getting Started Guide UG158 March 24
Version
Revision
ug000preface.fm to “Guide.”
Version
Revision
Updated tools for IP0K release
Version
Revision
10/10/07
Table of Contents
Preface About This Guide
Chapter 1 Getting Started
Chapter 2 Licensing the Core
Chapter 6 Implementing a Design
Chapter 7 Timing Simulation
Verilog VHDL Exemplar LeonardoSpectrum Xilinx XST
ISE Foundation
Schedule of Figures
Chapter 1 Getting Started Chapter 2 Licensing the Core
Chapter 4 Functional Simulation Chapter 5 Synthesizing a Design
Chapter 6 Implementing a Design Chapter 7 Timing Simulation
PCI-X v5.1 165 Getting Started Guide
UG158 March 24
Preface
Guide Contents
About This Guide
Conventions
Typographical
Preface About This Guide
Convention
Online Document
Conventions
See “Additional Resources”
Blue text
UG158 March 24
Preface About This Guide
PCI-X v5.1 165 Getting Started Guide
Getting Started
Chapter
System Requirements
About the Example Design
Additional Documentation
Technical Support
Feedback
Core Interface for PCI-X
Licensing the Core
Before you Begin
Licensing Options
Full System Hardware Evaluation
Installing Your License File
Full License
Direct Download
Obtaining a Full License
Family Specific Considerations
Design Support
Table 3-1 Device and Interface Selection
Supported Device
Chapter 3 Family Specific Considerations
Wrapper File
Table 3-1 Device and Interface Selection
Supported Device
Design Support Table 3-1 Device and Interface Selection
Wrapper File
Supported Device
Bus Type
Wrapper Files
Constraints Files
Chapter 3 Family Specific Considerations
Table 3-1 Device and Interface Selection
Configuration Pins
Bus Mode Detection
Device Initialization
Bus Width Detection
Bus Clock Usage
Table 3-2 Bitstream Requirements
Desired System Interface Implementation
Bitstreams
3.6 volts, as allowed by the PCI Local Bus Specification
Electrical Compliance
Electrical Compliance
Figure 3-1 PCI/PCI-X Output Driver VCCO Generation
Input Delay Buffers
Chapter 3 Family Specific Considerations
Generating Bitstreams
Generating Bitstreams
UG158 March 24
Chapter 3 Family Specific Considerations
PCI-X v5.1 165 Getting Started Guide
Chapter
Functional Simulation
Cadence IUS
Chapter 4 Functional Simulation
Mentor Graphics ModelSim
Verilog
VHDL
Mentor Graphics ModelSim
Chapter 4 Functional Simulation
vlib simprim
Synthesizing a Design
Synplicity Synplify
Figure 5-1 Create a New Project
Chapter
Chapter 5 Synthesizing a Design
Figure 5-2 Main Project Window
Figure 5-4 Files to Add LogiCORE Files
Synplicity Synplify
Figure 5-3 Files to Add Virtex Library
Figure 5-5 Files to Add User Application
Figure 5-6 Source Files in Main Project Window
Chapter 5 Synthesizing a Design
7. Navigate to the source directory Figure 5-5, select the cfgtests.v, pcixtop.v, and userapp.v files, and then click Add
Figure 5-7 Options for Implementation Device
Synplicity Synplify
10. Click Change Result File to display the EDIF Result File dialog box then move the to following directory
Figure 5-8 Options for Implementation Options/Constraints
Figure 5-9 Create a New Project
Install Path/vhdl/example/synthesis
VHDL
Chapter 5 Synthesizing a Design
Figure 5-10 Main Project Window
Figure 5-11 Files to Add Virtex Library
Synplicity Synplify
3. Click OK to exit the dialog and return to the project window Figure
Figure 5-12 Files to Add LogiCORE Files
Figure 5-13 Files to Add User Application
Install Path/vhdl/src/xpci
Install Path/vhdl/example/source
8. In the Source Files list, view the list of newly added source files by double-clicking the flowtest/vhdl folder if it is not already open. Drag to reorder the source files in the hierarchical order shown in Figure
Figure 5-14 Main Project Window
Synplicity Synplify
Chapter 5 Synthesizing a Design
Exemplar LeonardoSpectrum
Figure 5-15 Options for Implementation Device
Xilinx XST
Xilinx XST
UG158 March 24
Chapter 5 Synthesizing a Design
PCI-X v5.1 165 Getting Started Guide
Chapter
Implementing a Design
ISE Foundation
Chapter 6 Implementing a Design
Timing Simulation
cd Install Path/verilog/example/postsim cp ../xilinx/*.v
Chapter
Cadence IUS
Chapter 7 Timing Simulation
Mentor Graphics ModelSim
Verilog
VHDL
Install Path/vhdl/example/postsim
Mentor Graphics ModelSim
