R
Chapter 5: Synthesizing a Design
15.On the Implementation Results tab, deselect Write Vendor Constraint File.
16.Click OK to return to the main project window.
17.From the main project window, click Run.
Synplify synthesizes the design and writes out an optimized EDIF file. In the lower- right corner of the window, the various stages or synthesis, such as Compiling or Mapping, are displayed.
When the process is complete, Done is displayed. Synplify may issue a number of warnings (which are expected) about instantiated I/O cells and attributes used for other synthesis tools.
VHDL
1.Start Synplify and choose File > New (Figure
Figure 5-9: Create a New Project
2.Under File Type, select Project File and enter the project name (flowtest in this example) and synthesis directory:
<Install Path>/vhdl/example/synthesis
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| UG158 March 24, 2008 |
