Configuration Options, Jtag Configuration | Xilinx UG518 specification

Chapter 1: SP601 Evaluation Board

Configuration Options

The FPGA on the SP601 Evaluation Board can be configured by the following methods:

•“3. SPI x4 Flash,” page 18

•“4. Linear Flash BPI,” page 20

•“JTAG Configuration,” page 42

For more information, refer to the Spartan-6 FPGA Configuration User Guide. [Ref 2]

Table 1-23:Mode Pin Settings (M2 = 0)

Mode Pins (M1, M0)	Configuration Mode

00	Master Byte Peripheral Interface (BPI)

01	Master SPI x1, x2, or x4

10	Not implemented on SP601

11	Not implemented on SP601

JTAG Configuration

JTAG configuration is provided through onboard USB-to-JTAG configuration logic where a computer host accesses the SP601 JTAG chain through a Type-A (computer host side) to Type-Mini-B (SP601 side) USB cable.

The JTAG chain of the board is illustrated in Figure 1-31. JTAG configuration is allowable at any time under any mode pin setting. JTAG initiated configuration takes priority over the mode pin settings.

FMC bypass jumper J4 must be connected between pins 1-2 for JTAG access to the FPGA on the basic SP601 board, as shown in Figure 1-31. When the VITA 57.1 FMC expansion connector is populated with an expansion module that has a JTAG chain, then jumper J4 must be set to connect pins 2-3 in order to include the FMC expansion module's JTAG chain in the main SP601 JTAG chain.

J10

USB Mini-B Connector

FPGA

TDI TDO

U1

J4

1

FMC LPC Expansion

TDI

J1

TDO

*Default jumper setting excludes FMC. To include FMC, jumper pins 2-3.

UG518_31_070809

Figure 1-31: JTAG Chain

42	www.xilinx.com	SP601 Hardware User Guide
		UG518 (v1.1) August 19, 2009

Image 42

Xilinx UG518 manual Configuration Options, Jtag Configuration

Contents

SP601 Hardware User Guide UG518 v1.1 August 19, 2009 optional SP601 Hardware User Guide Revision History Date Version Revision SP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 Guide Contents About This GuideAdditional Resources Conventions Online Document Preface About This GuideMeaning or Use Example SP601 Evaluation Board OverviewAdditional Information Features SP601 Evaluation Board Block Diagram Related Xilinx DocumentsRelated Xilinx Documents SP601 Features FeatureDetailed Description Detailed Description SP601 Features Cont’d NumberSpartan-6 XC6SLX16-2CSG324 Fpga 2I/O Voltage Rail of Fpga Banks MB DDR2 Component Memory Schematic Netname Memory U2 5DDR2 Component Memory ConnectionsName 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins SPI x4 Flash 6J12 SPI Flash Programming Header Schematic Netname Pin # Linear Flash BPI 8UCF Location Constraints for BPI Flash Connections FLASHA6 10UCF Location Constraints for BPI Flash Connections 10/100/1000 Tri-Speed Ethernet PHY 8PHY Configuration PinsSchematic Netname U3 M88E111 Pin Bit2 Bit1 Bit0 Schematic Netname U3 M88E111 SP601 Evaluation Board 9PHY Connections Cont’d USB-to-UART Bridge CP2103GM Connections IIC Bus 13IIC Bus Topology Clock Generation 14UCF Location Constraints for IIC Connections Vita 57.1 FMC-LPC Connector 16UCF Location Constraints for Oscillator Socket Connections 13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Reference Signal Name Color Label Description Status LEDs Suspend Mode I/O Fpga Awake LED and Suspend Jumper Fpga Init and Done LEDs Controlled LED Reference Signal Name Color Label Fpga Pin User I/O User DIP switch Reference Signal Name Color Label Fpga Pin Designator User Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O AC Adapter and 5V Input Power Jack/Switch Power ManagementFpgaprogb Pushbutton Switch Onboard Power Supplies Power Management 22Estimated Current Draw Rail Estimated Current a Configuration Options Jtag Configuration Configuration Options 32VITA 57.1 FMC Jtag Bypass Jumper SP601 Evaluation Board References Appendix a References Default Jumper and Switch Settings Table B-1Default Jumper and Switch SettingsType/Function Default Appendix B Default Jumper and Switch Settings Vita 57.1 FMC Connections Table C-1VITA 57.1 FMC LPC ConnectionsLPC Pin FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn