Xilinx UG518 manual 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections

Models: UG518

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Detailed Description

NET "FMC_CLK0_M2C_N"

NET "FMC_CLK0_M2C_P"

NET "FMC_CLK1_M2C_N"

NET "FMC_CLK1_M2C_P"

NET "FMC_LA00_CC_N"

NET "FMC_LA00_CC_P"

NET "FMC_LA01_CC_N"

NET "FMC_LA01_CC_P" NET "FMC_LA02_N" NET "FMC_LA02_P" NET "FMC_LA03_N" NET "FMC_LA03_P" NET "FMC_LA04_N" NET "FMC_LA04_P" NET "FMC_LA05_N" NET "FMC_LA05_P" NET "FMC_LA06_N" NET "FMC_LA06_P" NET "FMC_LA07_N" NET "FMC_LA07_P" NET "FMC_LA08_N" NET "FMC_LA08_P" NET "FMC_LA09_N" NET "FMC_LA09_P" NET "FMC_LA10_N" NET "FMC_LA10_P" NET "FMC_LA11_N" NET "FMC_LA11_P" NET "FMC_LA12_N" NET "FMC_LA12_P" NET "FMC_LA13_N" NET "FMC_LA13_P" NET "FMC_LA14_N" NET "FMC_LA14_P" NET "FMC_LA15_N" NET "FMC_LA15_P" NET "FMC_LA16_N" NET "FMC_LA16_P" NET "FMC_LA17_CC_N" NET "FMC_LA17_CC_P" NET "FMC_LA18_CC_N" NET "FMC_LA18_CC_P" NET "FMC_LA19_N" NET "FMC_LA19_P" NET "FMC_LA20_N" NET "FMC_LA20_P" NET "FMC_LA21_N" NET "FMC_LA21_P" NET "FMC_LA22_N" NET "FMC_LA22_P" NET "FMC_LA23_N" NET "FMC_LA23_P" NET "FMC_LA24_N" NET "FMC_LA24_P" NET "FMC_LA25_N" NET "FMC_LA25_P" NET "FMC_LA26_N" NET "FMC_LA26_P" NET "FMC_LA27_N" NET "FMC_LA27_P" NET "FMC_LA28_N" NET "FMC_LA28_P" NET "FMC_LA29_N" NET "FMC_LA29_P" NET "FMC_LA30_N" NET "FMC_LA30_P" NET "FMC_LA31_N" NET "FMC_LA31_P" NET "FMC_LA32_N" NET "FMC_LA32_P" NET "FMC_LA33_N" NET "FMC_LA33_P"

NET "FMC_PRSNT_M2C_L"

NET "FMC_PWR_GOOD_FLASH_RST_B"

LOC = "A10"; LOC = "C10"; LOC = "V9"; LOC = "T9"; LOC = "C9"; LOC = "D9"; LOC = "C11"; LOC = "D11"; LOC = "A15"; LOC = "C15"; LOC = "A13"; LOC = "C13"; LOC = "A16"; LOC = "B16"; LOC = "A14"; LOC = "B14"; LOC = "C12"; LOC = "D12"; LOC = "E8"; LOC = "E7"; LOC = "E11"; LOC = "F11"; LOC = "F10"; LOC = "G11"; LOC = "C8"; LOC = "D8"; LOC = "A12"; LOC = "B12"; LOC = "C6"; LOC = "D6"; LOC = "A11"; LOC = "B11"; LOC = "A2"; LOC = "B2"; LOC = "F9"; LOC = "G9"; LOC = "A7"; LOC = "C7"; LOC = "T8"; LOC = "R8"; LOC = "T10"; LOC = "R10"; LOC = "P7"; LOC = "N6"; LOC = "P8"; LOC = "N7"; LOC = "V4"; LOC = "T4"; LOC = "T7"; LOC = "R7"; LOC = "P6"; LOC = "N5"; LOC = "V8"; LOC = "U8"; LOC = "N11"; LOC = "M11"; LOC = "V7"; LOC = "U7"; LOC = "T11"; LOC = "R11"; LOC = "V11"; LOC = "U11"; LOC = "N8"; LOC = "M8"; LOC = "V12"; LOC = "T12"; LOC = "V6"; LOC = "T6"; LOC = "V15"; LOC = "U15"; LOC = "N9"; LOC = "M10"; LOC = "U13"; LOC = "B3";

Figure 1-18:UCF Location Constraints for VITA 57.1 FMC-LPC Connections

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UG518 (v1.1) August 19, 2009

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Xilinx UG518 manual 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections