About This Guide, Guide Contents | Xilinx UG518 specification

Preface

About This Guide

This manual accompanies the Spartan®-6 FPGA SP601 Evaluation Board and contains information about the SP601 hardware and software tools.

Guide Contents

This manual contains the following chapters:

•Chapter 1, “SP601 Evaluation Board,” provides an overview of the embedded development board and details the components and features of the SP601 board.

•Appendix A, “References.”

•Appendix B, “Default Jumper and Switch Settings.”

•Appendix D, “SP601 Master UCF.”

Additional Resources

To search the database of silicon and software questions and answers, or to create a technical support case in WebCase, see the Xilinx website at: http://www.xilinx.com/support.

Conventions

This document uses the following conventions. An example illustrates each convention.

Typographical

The following typographical conventions are used in this document:

	Convention	Meaning or Use	Example

		Messages, prompts, and
	Courier font	program files that the system	speed grade: - 100
		displays

	Courier bold	Literal commands that you enter	ngdbuild design_name
		in a syntactical statement

		Commands that you select from	File → Open
	Helvetica bold	a menu	File → Open
		a menu


		Keyboard shortcuts	Ctrl+C

SP601 Hardware User Guide

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UG518 (v1.1) August 19, 2009

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Xilinx UG518 manual About This Guide, Guide Contents, Additional Resources Conventions

Contents

UG518 v1.1 August 19, 2009 optional SP601 Hardware User Guide SP601 Hardware User Guide Date Version Revision Revision History SP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 About This Guide Guide ContentsAdditional Resources Conventions Preface About This Guide Online DocumentMeaning or Use Example Overview SP601 Evaluation BoardAdditional Information SP601 Evaluation Board Features Related Xilinx Documents Block DiagramRelated Xilinx Documents Feature SP601 FeaturesDetailed Description 2I/O Voltage Rail of Fpga Banks SP601 Features Cont’d NumberSpartan-6 XC6SLX16-2CSG324 Fpga Detailed Description MB DDR2 Component Memory 5DDR2 Component Memory Connections Schematic Netname Memory U2Name 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins 6J12 SPI Flash Programming Header SPI x4 Flash Pin # Schematic Netname 8UCF Location Constraints for BPI Flash Connections Linear Flash BPI FLASHA6 10UCF Location Constraints for BPI Flash Connections Bit2 Bit1 Bit0 8PHY Configuration PinsSchematic Netname U3 M88E111 Pin 10/100/1000 Tri-Speed Ethernet PHY SP601 Evaluation Board 9PHY Connections Cont’d Schematic Netname U3 M88E111 CP2103GM Connections USB-to-UART Bridge 13IIC Bus Topology IIC Bus 14UCF Location Constraints for IIC Connections Clock Generation 16UCF Location Constraints for Oscillator Socket Connections Vita 57.1 FMC-LPC Connector 13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Status LEDs Reference Signal Name Color Label Description Fpga Awake LED and Suspend Jumper Suspend Mode I/O Controlled LED Fpga Init and Done LEDs User I/O Reference Signal Name Color Label Fpga Pin Reference Signal Name Color Label Fpga Pin Designator User DIP switch User Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Onboard Power Supplies Power ManagementFpgaprogb Pushbutton Switch AC Adapter and 5V Input Power Jack/Switch 22Estimated Current Draw Rail Estimated Current a Power Management Jtag Configuration Configuration Options 32VITA 57.1 FMC Jtag Bypass Jumper Configuration Options SP601 Evaluation Board References Appendix a References Table B-1Default Jumper and Switch Settings Default Jumper and Switch SettingsType/Function Default Appendix B Default Jumper and Switch Settings Table C-1VITA 57.1 FMC LPC Connections Vita 57.1 FMC ConnectionsLPC Pin FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn