13IIC Bus Topology | Xilinx UG518 instruction

Chapter 1: SP601 Evaluation Board

References

Technical information on the Silicon Labs CP2103GM and the VCP drivers can be found on their website at https://www.silabs.com/Pages/default.aspx.

In addition, see some of the Xilinx UART IP specifications at:

•http://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf

•http://www.xilinx.com/support/documentation/ip_documentation/xps_uartlite.pdf

•http://www.xilinx.com/support/documentation/ip_documentation/xps_uart16550.pdf

7.IIC Bus

The SP601 IIC bus hosts four items:

•FPGA U1 IIC interface

•2-pin IIC external access header

•8-Kb NV Memory

•VITA 57.1 FMC Connector J1

The SP601 IIC bus topology is shown in Figure 1-13.

U1

VITA 57.1		FMC-LPC
FMC-LPC		GA0=1
	J1	GA1=0
	J1
C30	C31

U7

FPGA IIC

INTERFACE

IIC_SDA_MAIN

IIC_SCL_MAIN

2 1

J16

IIC EXTERNAL

ACCESS

CONNECTOR

ST MICRO

M24 C08-WDW6TP

Address range

54-56

0b1010100-

0b1010110

UG518_13_070809

Figure 1-13:IIC Bus Topology

The IIC Bus on the SP601 provides access to a 2-pin header, the onboard 8-Kb EEPROM, and the VITA 57.1 FMC interface. The user must ensure there are no IIC address conflicts with the onboard EEPROM address when attaching additional IIC devices via FMC or the IIC 2-pin header. Note that FMC Mezzanine cards are designed with 2-Kb IIC EEPROMs and will not conflict with the Carrier Card (SP601) 8-Kb EEPROM address range. This is because 2-Kb EEPROMs reside below the 8-Kb EEPROM space. See the VITA 57.1 specification along with any IIC 2-Kbit EEPROM data sheet for more details.

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		UG518 (v1.1) August 19, 2009

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Xilinx UG518 manual 13IIC Bus Topology

Contents

SP601 Hardware User Guide UG518 v1.1 August 19, 2009 optional SP601 Hardware User Guide Revision History Date Version Revision SP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 Additional Resources Conventions Guide ContentsAbout This Guide Meaning or Use Example Online DocumentPreface About This Guide Additional Information SP601 Evaluation BoardOverview Features SP601 Evaluation Board Related Xilinx Documents Block DiagramRelated Xilinx Documents Detailed Description SP601 FeaturesFeature Detailed Description SP601 Features Cont’d NumberSpartan-6 XC6SLX16-2CSG324 Fpga 2I/O Voltage Rail of Fpga Banks MB DDR2 Component Memory Name Schematic Netname Memory U25DDR2 Component Memory Connections 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins SPI x4 Flash 6J12 SPI Flash Programming Header Schematic Netname Pin # Linear Flash BPI 8UCF Location Constraints for BPI Flash Connections FLASHA6 10UCF Location Constraints for BPI Flash Connections 10/100/1000 Tri-Speed Ethernet PHY 8PHY Configuration PinsSchematic Netname U3 M88E111 Pin Bit2 Bit1 Bit0 Schematic Netname U3 M88E111 SP601 Evaluation Board 9PHY Connections Cont’d USB-to-UART Bridge CP2103GM Connections IIC Bus 13IIC Bus Topology Clock Generation 14UCF Location Constraints for IIC Connections Vita 57.1 FMC-LPC Connector 16UCF Location Constraints for Oscillator Socket Connections 13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Reference Signal Name Color Label Description Status LEDs Suspend Mode I/O Fpga Awake LED and Suspend Jumper Fpga Init and Done LEDs Controlled LED Reference Signal Name Color Label Fpga Pin User I/O User DIP switch Reference Signal Name Color Label Fpga Pin Designator User Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O AC Adapter and 5V Input Power Jack/Switch Power ManagementFpgaprogb Pushbutton Switch Onboard Power Supplies Power Management 22Estimated Current Draw Rail Estimated Current a Configuration Options Jtag Configuration Configuration Options 32VITA 57.1 FMC Jtag Bypass Jumper SP601 Evaluation Board References Appendix a References Type/Function Default Default Jumper and Switch SettingsTable B-1Default Jumper and Switch Settings Appendix B Default Jumper and Switch Settings LPC Pin Vita 57.1 FMC ConnectionsTable C-1VITA 57.1 FMC LPC Connections FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn