Clock Generation | Xilinx UG518 specification

Detailed Description

8-Kb NV Memory

The SP601 hosts a 8-Kb ST Microelectronics M24C08-WDW6TP IIC parameter storage memory device (U7). The IIC address of U7 is 0b1010100, and U7 is not write protected (WP pin 7 is tied to GND).

Table 1-12:IIC Memory Connections

	FPGA U1 Pin	Schematic Netname		SPI Memory U7
	FPGA U1 Pin
	Number
				Pin Number	Pin



	Not Applicable	Tied to GND		1	A0

	Not Applicable	Tied to GND		2	A1

	Not Applicable	Pulled up (0 ohm) to VCC3V3		3	A2

	N10	IIC_SDA_MAIN		5	SDA

	P11	IIC_SCL_MAIN		6	SCL

	Not Applicable	Tied to GND		7	WP

	NET "IIC_SCL_MAIN"		LOC = "P11";
	NET "IIC_SDA_MAIN"		LOC = "N10";

Figure 1-14:UCF Location Constraints for IIC Connections

References

See the ST Micro M24C08-WDW6TP data sheet for more information at

http://www.st.com/stonline/products/literature/ds/5067/m24c08-w.pdf.

In addition, see the Xilinx XPS IIC Bus Interface specification at

http://www.xilinx.com/support/documentation/ip_documentation/xps_iic.pdf.

Also, see “9. VITA 57.1 FMC-LPC Connector,” page 28.

8. Clock Generation

There are three clock sources available on the SP601.

Oscillator (Differential)

The SP601 has one 2.5V LVDS differential 200 MHz oscillator (U5) soldered onto the board and wired to an FPGA global clock input.

•Crystal oscillator: Epson EG2121CA

•PPM frequency jitter: 50 ppm

NET	"SYSCLK_N"	LOC	=	"K16";
NET	"SYSCLK_P"	LOC	=	"K15";

Figure 1-15:UCF Location Constraints for Oscillator Connections

References

For more details, see the Epson data sheet at http://www.epsontoyocom.co.jp/english/product/OSC/set04/eg2121ca/index.html.

SP601 Hardware User Guide

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UG518 (v1.1) August 19, 2009

Image 27

Xilinx UG518 manual Clock Generation, 14UCF Location Constraints for IIC Connections

Contents

UG518 v1.1 August 19, 2009 optional SP601 Hardware User Guide SP601 Hardware User Guide Date Version Revision Revision History SP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 Guide Contents About This GuideAdditional Resources Conventions Online Document Preface About This GuideMeaning or Use Example SP601 Evaluation Board OverviewAdditional Information SP601 Evaluation Board Features Block Diagram Related Xilinx DocumentsRelated Xilinx Documents SP601 Features FeatureDetailed Description 2I/O Voltage Rail of Fpga Banks SP601 Features Cont’d NumberSpartan-6 XC6SLX16-2CSG324 Fpga Detailed Description MB DDR2 Component Memory Schematic Netname Memory U2 5DDR2 Component Memory ConnectionsName 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins 6J12 SPI Flash Programming Header SPI x4 Flash Pin # Schematic Netname 8UCF Location Constraints for BPI Flash Connections Linear Flash BPI FLASHA6 10UCF Location Constraints for BPI Flash Connections Bit2 Bit1 Bit0 8PHY Configuration PinsSchematic Netname U3 M88E111 Pin 10/100/1000 Tri-Speed Ethernet PHY SP601 Evaluation Board 9PHY Connections Cont’d Schematic Netname U3 M88E111 CP2103GM Connections USB-to-UART Bridge 13IIC Bus Topology IIC Bus 14UCF Location Constraints for IIC Connections Clock Generation 16UCF Location Constraints for Oscillator Socket Connections Vita 57.1 FMC-LPC Connector 13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Status LEDs Reference Signal Name Color Label Description Fpga Awake LED and Suspend Jumper Suspend Mode I/O Controlled LED Fpga Init and Done LEDs User I/O Reference Signal Name Color Label Fpga Pin Reference Signal Name Color Label Fpga Pin Designator User DIP switch User Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Onboard Power Supplies Power ManagementFpgaprogb Pushbutton Switch AC Adapter and 5V Input Power Jack/Switch 22Estimated Current Draw Rail Estimated Current a Power Management Jtag Configuration Configuration Options 32VITA 57.1 FMC Jtag Bypass Jumper Configuration Options SP601 Evaluation Board References Appendix a References Default Jumper and Switch Settings Table B-1Default Jumper and Switch SettingsType/Function Default Appendix B Default Jumper and Switch Settings Vita 57.1 FMC Connections Table C-1VITA 57.1 FMC LPC ConnectionsLPC Pin FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn