Appendix D: SP601 Master UCF

NET "FPGA_CMP_MOSI"

LOC = "V16";

NET "FPGA_D0_DIN_MISO_MISO1"

LOC = "R13";

NET "FPGA_D1_MISO2"

LOC = "T14";

NET "FPGA_D2_MISO3"

LOC = "V14";

NET "FPGA_DONE"

LOC = "V17";

NET "FPGA_HSWAPEN"

LOC = "D4";

NET "FPGA_INIT_B"

LOC = "U3";

NET "FPGA_M0_CMP_MISO"

LOC = "T15";

NET "FPGA_M1"

LOC = "N12";

NET "FPGA_MOSI_CSI_B_MISO0"

LOC = "T13";

NET "FPGA_ONCHIP_TERM1"

LOC = "L6";

NET "FPGA_ONCHIP_TERM2"

LOC = "C2";

NET "FPGA_PROG_B"

LOC = "V2";

NET "FPGA_SUSPEND"

LOC = "R16";

NET "FPGA_TCK_BUF"

LOC = "A17";

NET "FPGA_TDI_BUF"

LOC = "D15";

NET "FPGA_TDO"

LOC = "D16";

NET "FPGA_TMS_BUF"

LOC = "B18";

NET "FPGA_VTEMP"

LOC = "P3";

NET "GPIO_BUTTON0"

LOC = "P4";

NET "GPIO_BUTTON1"

LOC = "F6";

NET "GPIO_BUTTON2"

LOC = "E4";

NET "GPIO_BUTTON3"

LOC = "F5";

NET "GPIO_HDR0"

LOC = "N17";

NET "GPIO_HDR1"

LOC = "M18";

NET "GPIO_HDR2"

LOC = "A3";

NET "GPIO_HDR3"

LOC = "L15";

NET "GPIO_HDR4"

LOC = "F15";

NET "GPIO_HDR5"

LOC = "B4";

NET "GPIO_HDR6"

LOC = "F13";

NET "GPIO_HDR7"

LOC = "P12";

NET "GPIO_LED_0"

LOC = "E13";

NET "GPIO_LED_1"

LOC = "C14";

NET "GPIO_LED_2"

LOC = "C4";

NET "GPIO_LED_3"

LOC = "A4";

NET "GPIO_SWITCH_0"

LOC = "D14";

NET "GPIO_SWITCH_1"

LOC = "E12";

NET "GPIO_SWITCH_2"

LOC = "F12";

NET "GPIO_SWITCH_3"

LOC = "V13";

NET "IIC_SCL_MAIN"

LOC = "P11";

NET "IIC_SDA_MAIN"

LOC = "N10";

NET "PHY_COL"

LOC = "L14";

NET "PHY_CRS"

LOC = "M13";

NET "PHY_INT"

LOC = "J13";

NET "PHY_MDC"

LOC = "N14";

NET "PHY_MDIO"

LOC = "P16";

NET "PHY_RESET"

LOC = "L13";

NET "PHY_RXCLK"

LOC = "L16";

NET "PHY_RXCTL_RXDV"

LOC = "N18";

NET "PHY_RXD0"

LOC = "M14";

NET "PHY_RXD1"

LOC = "U18";

NET "PHY_RXD2"

LOC = "U17";

NET "PHY_RXD3"

LOC = "T18";

NET "PHY_RXD4"

LOC = "T17";

NET "PHY_RXD5"

LOC = "N16";

NET "PHY_RXD6"

LOC = "N15";

NET "PHY_RXD7"

LOC = "P18";

NET "PHY_RXER"

LOC = "P17";

NET "PHY_TXCLK"

LOC = "B9";

54

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SP601 Hardware User Guide

 

 

UG518 (v1.1) August 19, 2009

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Xilinx UG518 manual NET Fpgacmpmosi