10/100/1000 Tri-Speed Ethernet PHY, Bit2 Bit1 Bit0 | Xilinx UG518

Detailed Description

5. 10/100/1000 Tri-Speed Ethernet PHY

The SP601 uses the onboard Marvell Alaska PHY device (88E1111) for Ethernet communications at 10, 100, or 1000 Mb/s. The board supports a GMII/MII interface from the FPGA to the PHY. The PHY connection to a user-provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector with built-in magnetics.

On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY address 0b00111 using the settings shown in Table 1-8. These settings can be overwritten via software commands passed over the MDIO interface.

Table 1-8:PHY Configuration Pins

Pin	Connection on			Bit[2]			Bit[1]	Bit[0]
Pin		Board	Definition and Value			Definition and Value		Definition and Value
		Board	Definition and Value			Definition and Value		Definition and Value

CFG0		VCC 2.5V		PHYADR[2] = 1		PHYADR[1] = 1		PHYADR[0] = 1
CFG1		Ground		ENA_PAUSE = 0		PHYADR[4] = 0		PHYADR[3] = 0

CFG2		VCC 2.5V		ANEG[3] = 1		ANEG[2] = 1		ANEG[1] = 1
CFG3		VCC 2.5V		ANEG[0] = 1		ENA_XC = 1		DIS_125 = 1
CFG4		VCC 2.5V		HWCFG_MD[2] = 1		HWCFG_MD[1] = 1		HWCFG_MD[0] = 1
CFG5		VCC 2.5V		DIS_FC = 1		DIS_SLEEP = 1		HWCFG_MD[3] = 1
CFG6	PHY_LED_RX			SEL_BDT = 0		INT_POL = 1		75/50 OHM = 0

Table 1-9:PHY Connections

FPGA U1		Schematic Netname			U3 M88E111
Pin		Schematic Netname			U3 M88E111
Pin

P16		PHY_MDIO			33

N14		PHY_MDC			35

J13		PHY_INT			32

L13		PHY_RESET			36

M13		PHY_CRS			115

L14		PHY_COL			114

L16		PHY_RXCLK			7

P17		PHY_RXER			8

N18		PHY_RXCTL_RXDV			4

M14		PHY_RXD0			3

U18		PHY_RXD1			128

U17		PHY_RXD2			126

T18		PHY_RXD3			125

T17		PHY_RXD4			124

N16		PHY_RXD5			123

N15		PHY_RXD6			121

SP601 Hardware User Guide

www.xilinx.com

23

UG518 (v1.1) August 19, 2009

Image 23

Xilinx UG518 manual 10/100/1000 Tri-Speed Ethernet PHY, 8PHY Configuration Pins, Bit2 Bit1 Bit0, PHY Connections

Contents

UG518 v1.1 August 19, 2009 optional SP601 Hardware User Guide SP601 Hardware User Guide Date Version Revision Revision History SP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 Additional Resources Conventions Guide ContentsAbout This Guide Meaning or Use Example Online DocumentPreface About This Guide Additional Information SP601 Evaluation BoardOverview SP601 Evaluation Board Features Related Xilinx Documents Block DiagramRelated Xilinx Documents Detailed Description SP601 FeaturesFeature 2I/O Voltage Rail of Fpga Banks SP601 Features Cont’d NumberSpartan-6 XC6SLX16-2CSG324 Fpga Detailed Description MB DDR2 Component Memory Name Schematic Netname Memory U25DDR2 Component Memory Connections 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins 6J12 SPI Flash Programming Header SPI x4 Flash Pin # Schematic Netname 8UCF Location Constraints for BPI Flash Connections Linear Flash BPI FLASHA6 10UCF Location Constraints for BPI Flash Connections Bit2 Bit1 Bit0 8PHY Configuration PinsSchematic Netname U3 M88E111 Pin 10/100/1000 Tri-Speed Ethernet PHY SP601 Evaluation Board 9PHY Connections Cont’d Schematic Netname U3 M88E111 CP2103GM Connections USB-to-UART Bridge 13IIC Bus Topology IIC Bus 14UCF Location Constraints for IIC Connections Clock Generation 16UCF Location Constraints for Oscillator Socket Connections Vita 57.1 FMC-LPC Connector 13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Status LEDs Reference Signal Name Color Label Description Fpga Awake LED and Suspend Jumper Suspend Mode I/O Controlled LED Fpga Init and Done LEDs User I/O Reference Signal Name Color Label Fpga Pin Reference Signal Name Color Label Fpga Pin Designator User DIP switch User Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Onboard Power Supplies Power ManagementFpgaprogb Pushbutton Switch AC Adapter and 5V Input Power Jack/Switch 22Estimated Current Draw Rail Estimated Current a Power Management Jtag Configuration Configuration Options 32VITA 57.1 FMC Jtag Bypass Jumper Configuration Options SP601 Evaluation Board References Appendix a References Type/Function Default Default Jumper and Switch SettingsTable B-1Default Jumper and Switch Settings Appendix B Default Jumper and Switch Settings LPC Pin Vita 57.1 FMC ConnectionsTable C-1VITA 57.1 FMC LPC Connections FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn