LPC Pinout Cont’d | Xilinx UG518 manual

Chapter 1: SP601 Evaluation Board

Table 1-13: LPC Pinout (Cont’d)

	K	J	H	G	F	E	D	C	B	A

34	NC	NC	LA30_P	LA31_N	NC	NC	TRST_L	GA0	NC	NC

35	NC	NC	LA30_N	GND	NC	NC	GA1	12P0V	NC	NC

36	NC	NC	GND	LA33_P	NC	NC	3P3V	GND	NC	NC

37	NC	NC	LA32_P	LA33_N	NC	NC	GND	12P0V	NC	NC

38	NC	NC	LA32_N	GND	NC	NC	3P3V	GND	NC	NC

39	NC	NC	GND	VADJ	NC	NC	GND	3P3V	NC	NC

40	NC	NC	VADJ	GND	NC	NC	3P3V	GND	NC	NC

30	www.xilinx.com	SP601 Hardware User Guide
		UG518 (v1.1) August 19, 2009

Image 30

Xilinx UG518 manual LPC Pinout Cont’d

Contents

SP601 Hardware User Guide UG518 v1.1 August 19, 2009 optional SP601 Hardware User Guide Revision History Date Version Revision SP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 Guide Contents About This GuideAdditional Resources Conventions Online Document Preface About This GuideMeaning or Use Example SP601 Evaluation Board OverviewAdditional Information Features SP601 Evaluation Board Block Diagram Related Xilinx DocumentsRelated Xilinx Documents SP601 Features FeatureDetailed Description Detailed Description SP601 Features Cont’d NumberSpartan-6 XC6SLX16-2CSG324 Fpga 2I/O Voltage Rail of Fpga Banks MB DDR2 Component Memory Schematic Netname Memory U2 5DDR2 Component Memory ConnectionsName 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins SPI x4 Flash 6J12 SPI Flash Programming Header Schematic Netname Pin # Linear Flash BPI 8UCF Location Constraints for BPI Flash Connections FLASHA6 10UCF Location Constraints for BPI Flash Connections 10/100/1000 Tri-Speed Ethernet PHY 8PHY Configuration PinsSchematic Netname U3 M88E111 Pin Bit2 Bit1 Bit0 Schematic Netname U3 M88E111 SP601 Evaluation Board 9PHY Connections Cont’d USB-to-UART Bridge CP2103GM Connections IIC Bus 13IIC Bus Topology Clock Generation 14UCF Location Constraints for IIC Connections Vita 57.1 FMC-LPC Connector 16UCF Location Constraints for Oscillator Socket Connections 13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Reference Signal Name Color Label Description Status LEDs Suspend Mode I/O Fpga Awake LED and Suspend Jumper Fpga Init and Done LEDs Controlled LED Reference Signal Name Color Label Fpga Pin User I/O User DIP switch Reference Signal Name Color Label Fpga Pin Designator User Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O AC Adapter and 5V Input Power Jack/Switch Power ManagementFpgaprogb Pushbutton Switch Onboard Power Supplies Power Management 22Estimated Current Draw Rail Estimated Current a Configuration Options Jtag Configuration Configuration Options 32VITA 57.1 FMC Jtag Bypass Jumper SP601 Evaluation Board References Appendix a References Default Jumper and Switch Settings Table B-1Default Jumper and Switch SettingsType/Function Default Appendix B Default Jumper and Switch Settings Vita 57.1 FMC Connections Table C-1VITA 57.1 FMC LPC ConnectionsLPC Pin FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn