Xilinx UG518 - page 30

30 www.xilinx.com SP601 Hardware User Guide

UG518 (v1.1) August 19, 2009

Chapter 1: SP601 Evaluati on Board

34 NC NC LA30_P LA31_N NC NC TRST_L GA0 NC NC

35 NC NC LA30_N GND NC NC GA1 12P0V NC NC

36 NC NC GND LA33_P NC NC 3P3V GND NC NC

37 NC NC LA32_P LA33_N NC NC GND 12P0V NC NC

38 NC NC LA32_N GND NC NC 3P3V GND NC NC

39 NC NC GND VADJ NC NC GND 3P3V NC NC

40 NC NC VADJ GND NC NC 3P3V GND NC NC

Table 1-13: LPC Pinout (Cont’d)

KJ H G FE D C BA

Contents

Main SP601 Hardware User Guide www.xilinx.com UG518 (v1.1) August 19, 2009 Revision History The following table shows the revision history for this document. Page Table of Contents Preface: About This Guide Guide Contents Additional Resources Conventions Chapter 1: SP601 Evaluation Board Overview Page Preface About This Guide Guide Contents Additional Resources Conventions Typographical Online Document The following conventions are used in this document: Chapter 1 SP601 Evaluation Board Overview Additional Information Features Block Diagram Related Xilinx Documents Spartan-6 Detailed Description 1. Spartan-6 XC6SLX16-2CSG324 FPGA Configuration I/O Voltage Rails 2. 128 MB DDR2 Component Memory Page Figure 1-3: UCF Location Constraints for DDR2 SDRAM Address Inputs Table 1-5: DDR2 Component Memory Connections (Contd) Page 3. SPI x4 Flash Silkscreen Page 4. Linear Flash BPI U1 U10 Table 1-7: BPI Memory Connections (Contd) 22 www.xilinx.com SP601 Hardware User Guide UG518 (v1.1) August 19, 2009 Note: for larger density devices. Figure 1-10: UCF Location Constraints for BPI Flash Connections L17 FLASH_CE_B 14 CE0 B3 FMC_PWR_GOOD_FLASH_RST_B 16 RP_B Table 1-7: BPI Memory Connections (Contd) 5. 10/100/1000 Tri-Speed Ethernet PHY Figure 1-11: UCF Location Constraints for PHY Connections Table 1-9: PHY Connections (Contd) 6. USB-to-UART Bridge 7. IIC Bus 8-Kb NV Memory 8. Clock Generation Oscillator (Differential) Oscillator Socket (Single-Ended, 2.5V or 3.3V) SMA Connectors (Differential) 9. VITA 57.1 FMC-LPC Connector Table 1-13: LPC Pinout Page Figure 1-18: UCF Location Constraints for VITA 57.1 FMC-LPC Connections SP601 Hardware User Guide www.xilinx.com 31 UG518 (v1.1) August 19, 2009 10. Status LEDs 11. FPGA Awake LED and Suspend Jumper 12. FPGA INIT and DONE LEDs Figure 1-22: UCF Location Constraints for FPGA INIT and DONE FPGA DONE Figure 1-21: FPGA INIT and DONE LEDs INIT_B = 0, LED: ON INIT_B = 1, LED: OFF FPGA INIT B 13. User I/O User LEDs GPIO LED 3 GPIO LED 2 GPIO LED 1 GPIO LED 0 User DIP switch Figure 1-24: User DIP Switch DS13 GPIO_LED_2 Green C4 DS14 GPIO_LED_3 Green A4 Table 1-17: User LEDs (Contd) Reference Designator Signal Name Color Label FPGA Pin User Pushbutton Switches GPIO Male Pin Header Figure 1-26: GPIO Male Pin Header Topology J13 Table 1-20: GPIO Header Pins Figure 1-27: UCF Location Constraints for User and General-Purpose I/O 14. FPGA_PROG_B Pushbutton Switch Pushbutton 2 P3 Power Management AC Adapter and 5V Input Power Jack/Switch Onboard Power Supplies 1 2 1 P4 Figure 1-30: Power Supply Table 1-22: Estimated Current Draw Configuration Options JTAG Configuration Page Page Appendix A References Page Appendix B Default Jumper and Switch Settings Page Appendix C VITA 57.1 FMC Connections Tabl e C-1 shows the VITA 57.1 FMC LPC connections. Table C-1: VITA 57.1 FMC LPC Connections Appendix C: VITA 57.1 FMC Connections Table C-1: VITA 57.1 FMC LPC Connections (Contd) Appendix D SP601 Master UCF Page Page Appendix D: SP601 Master UCF