Detailed Description, SP601 Features | Xilinx UG518 specification

Chapter 1: SP601 Evaluation Board

Detailed Description

Figure 1-2shows a board photo with numbered features corresponding to Table 1-1and the section headings in this document.

14

15

9

21

7 11

8

5

10

6

13

8

16

4

3

12

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Figure 1-2:SP601 Board Photo

The numbered features in Figure 1-2correlate to the features and notes listed in Table 1-1.

Table 1-1:		SP601 Features

Number		Feature	Notes	Schematic
Number		Feature	Notes	Page
				Page

1		Spartan-6 FPGA	XC6SLX16-2CSG324

2		DDR2 Component	Hard memory controller w/ OCT	5

3		SPI x4 Flash and Headers	SPI select and External Headers	8

4		Linear Flash BPI	StrataFlash 8-bit (J3 device), 3 pins	8
			shared w/ SPI x4

5		10/100/1000 Ethernet PHY	GMII Marvell Alaska PHY	7

6		RS232 UART (USB Bridge)	Uses CP2103 Serial-to-USB connection	10

7		IIC	Goes to Header and VITA 57.1 FMC	10

8		Clock, socket, SMA	Differential, Single-Ended, Differential	9

12	www.xilinx.com	SP601 Hardware User Guide
		UG518 (v1.1) August 19, 2009

Image 12

Xilinx UG518 manual Detailed Description, SP601 Features

Contents

SP601 Hardware User Guide UG518 v1.1 August 19, 2009 optional SP601 Hardware User Guide Revision History Date Version Revision SP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 Guide Contents About This GuideAdditional Resources Conventions Online Document Preface About This GuideMeaning or Use Example SP601 Evaluation Board OverviewAdditional Information Features SP601 Evaluation Board Block Diagram Related Xilinx DocumentsRelated Xilinx Documents SP601 Features FeatureDetailed Description SP601 Features Cont’d Number Spartan-6 XC6SLX16-2CSG324 FpgaDetailed Description 2I/O Voltage Rail of Fpga Banks MB DDR2 Component Memory Schematic Netname Memory U2 5DDR2 Component Memory ConnectionsName 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins SPI x4 Flash 6J12 SPI Flash Programming Header Schematic Netname Pin # Linear Flash BPI 8UCF Location Constraints for BPI Flash Connections FLASHA6 10UCF Location Constraints for BPI Flash Connections 8PHY Configuration Pins Schematic Netname U3 M88E111 Pin10/100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0 Schematic Netname U3 M88E111 SP601 Evaluation Board 9PHY Connections Cont’d USB-to-UART Bridge CP2103GM Connections IIC Bus 13IIC Bus Topology Clock Generation 14UCF Location Constraints for IIC Connections Vita 57.1 FMC-LPC Connector 16UCF Location Constraints for Oscillator Socket Connections 13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Reference Signal Name Color Label Description Status LEDs Suspend Mode I/O Fpga Awake LED and Suspend Jumper Fpga Init and Done LEDs Controlled LED Reference Signal Name Color Label Fpga Pin User I/O User DIP switch Reference Signal Name Color Label Fpga Pin Designator User Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Power Management Fpgaprogb Pushbutton SwitchAC Adapter and 5V Input Power Jack/Switch Onboard Power Supplies Power Management 22Estimated Current Draw Rail Estimated Current a Configuration Options Jtag Configuration Configuration Options 32VITA 57.1 FMC Jtag Bypass Jumper SP601 Evaluation Board References Appendix a References Default Jumper and Switch Settings Table B-1Default Jumper and Switch SettingsType/Function Default Appendix B Default Jumper and Switch Settings Vita 57.1 FMC Connections Table C-1VITA 57.1 FMC LPC ConnectionsLPC Pin FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn