Xilinx UG518 manual Appendix D SP601 Master UCF

Models: UG518

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Appendix D: SP601 Master UCF

NET "DDR2_LDQS_P" NET "DDR2_ODT" NET "DDR2_RAS_B" NET "DDR2_UDM" NET "DDR2_UDQS_N" NET "DDR2_UDQS_P" NET "DDR2_WE_B" NET "FLASH_A0" NET "FLASH_A1" NET "FLASH_A2" NET "FLASH_A3" NET "FLASH_A4" NET "FLASH_A5" NET "FLASH_A6" NET "FLASH_A7" NET "FLASH_A8" NET "FLASH_A9" NET "FLASH_A10" NET "FLASH_A11" NET "FLASH_A12" NET "FLASH_A13" NET "FLASH_A14" NET "FLASH_A15" NET "FLASH_A16" NET "FLASH_A17" NET "FLASH_A18" NET "FLASH_A19" NET "FLASH_A20" NET "FLASH_A21" NET "FLASH_A22" NET "FLASH_A23" NET "FLASH_A24" NET "FLASH_CE_B" NET "FLASH_D3" NET "FLASH_D4" NET "FLASH_D5" NET "FLASH_D6" NET "FLASH_D7" NET "FLASH_OE_B" NET "FLASH_WE_B"

NET "FMC_CLK0_M2C_N" NET "FMC_CLK0_M2C_P" NET "FMC_CLK1_M2C_N" NET "FMC_CLK1_M2C_P" NET "FMC_LA00_CC_N" NET "FMC_LA00_CC_P" NET "FMC_LA01_CC_N" NET "FMC_LA01_CC_P" NET "FMC_LA02_N"

NET "FMC_LA02_P" NET "FMC_LA03_N" NET "FMC_LA03_P" NET "FMC_LA04_N" NET "FMC_LA04_P" NET "FMC_LA05_N" NET "FMC_LA05_P" NET "FMC_LA06_N" NET "FMC_LA06_P" NET "FMC_LA07_N"

LOC = "L4"; LOC = "K6"; LOC = "L5"; LOC = "K4"; LOC = "P1"; LOC = "P2"; LOC = "E3"; LOC = "K18"; LOC = "K17"; LOC = "J18"; LOC = "J16"; LOC = "G18"; LOC = "G16"; LOC = "H16"; LOC = "H15"; LOC = "H14"; LOC = "H13"; LOC = "F18"; LOC = "F17"; LOC = "K13"; LOC = "K12"; LOC = "E18"; LOC = "E16"; LOC = "G13"; LOC = "H12"; LOC = "D18"; LOC = "D17"; LOC = "G14"; LOC = "F14"; LOC = "C18"; LOC = "C17"; LOC = "F16"; LOC = "L17"; LOC = "U5"; LOC = "V5"; LOC = "R3"; LOC = "T3"; LOC = "R5"; LOC = "L18"; LOC = "M16"; LOC = "A10"; LOC = "C10"; LOC = "V9"; LOC = "T9"; LOC = "C9"; LOC = "D9"; LOC = "C11"; LOC = "D11"; LOC = "A15"; LOC = "C15"; LOC = "A13"; LOC = "C13"; LOC = "A16"; LOC = "B16"; LOC = "A14"; LOC = "B14"; LOC = "C12"; LOC = "D12"; LOC = "E8";

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SP601 Hardware User Guide

 

 

UG518 (v1.1) August 19, 2009

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Xilinx UG518 manual Appendix D SP601 Master UCF