FLASHA6 | Xilinx UG518 instruction

Detailed Description

Table 1-7:BPI Memory Connections (Cont’d)

	FPGA U1 Pin	Schematic Netname	BPI Memory U10

			Pin Number	Pin
			Pin Number	Pin

	H16	FLASH_A6	23	A6

	H15	FLASH_A7	22	A7

	H14	FLASH_A8	20	A8

	H13	FLASH_A9	19	A9

	F18	FLASH_A10	18	A10

	F17	FLASH_A11	17	A11

	K13	FLASH_A12	13	A12

	K12	FLASH_A13	12	A13

	E18	FLASH_A14	11	A14

	E16	FLASH_A15	10	A15

	G13	FLASH_A16	8	A16

	H12	FLASH_A17	7	A17

	D18	FLASH_A18	6	A18

	D17	FLASH_A19	5	A19

	G14	FLASH_A20	4	A20

	F14	FLASH_A21	3	A21

	C18	FLASH_A22	1	A22

	C17	FLASH_A23	30	A23

	F16	FLASH_A24	56	A24


	R13	FPGA_D0_DIN_MISO_MISO1	33	DQ0

	T14	FPGA_D1_MISO2	35	DQ1

	V14	FPGA_D2_MISO3	38	DQ2

	U5	FLASH_D3	40	DQ3

	V5	FLASH_D4	44	DQ4

	R3	FLASH_D5	46	DQ5

	T3	FLASH_D6	49	DQ6

	R5	FLASH_D7	51	DQ7


	M16	FLASH_WE_B	55	WE_B

	L18	FLASH_OE_B	54	OE_B

SP601 Hardware User Guide

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UG518 (v1.1) August 19, 2009

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Xilinx UG518 manual FLASHA6

Contents

UG518 v1.1 August 19, 2009 optional SP601 Hardware User Guide SP601 Hardware User Guide Date Version Revision Revision History SP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 Guide Contents About This GuideAdditional Resources Conventions Online Document Preface About This GuideMeaning or Use Example SP601 Evaluation Board OverviewAdditional Information SP601 Evaluation Board Features Block Diagram Related Xilinx DocumentsRelated Xilinx Documents SP601 Features FeatureDetailed Description Spartan-6 XC6SLX16-2CSG324 Fpga SP601 Features Cont’d NumberDetailed Description 2I/O Voltage Rail of Fpga Banks MB DDR2 Component Memory Schematic Netname Memory U2 5DDR2 Component Memory ConnectionsName 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins 6J12 SPI Flash Programming Header SPI x4 Flash Pin # Schematic Netname 8UCF Location Constraints for BPI Flash Connections Linear Flash BPI FLASHA6 10UCF Location Constraints for BPI Flash Connections Schematic Netname U3 M88E111 Pin 8PHY Configuration Pins10/100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0 SP601 Evaluation Board 9PHY Connections Cont’d Schematic Netname U3 M88E111 CP2103GM Connections USB-to-UART Bridge 13IIC Bus Topology IIC Bus 14UCF Location Constraints for IIC Connections Clock Generation 16UCF Location Constraints for Oscillator Socket Connections Vita 57.1 FMC-LPC Connector 13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Status LEDs Reference Signal Name Color Label Description Fpga Awake LED and Suspend Jumper Suspend Mode I/O Controlled LED Fpga Init and Done LEDs User I/O Reference Signal Name Color Label Fpga Pin Reference Signal Name Color Label Fpga Pin Designator User DIP switch User Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Fpgaprogb Pushbutton Switch Power ManagementAC Adapter and 5V Input Power Jack/Switch Onboard Power Supplies 22Estimated Current Draw Rail Estimated Current a Power Management Jtag Configuration Configuration Options 32VITA 57.1 FMC Jtag Bypass Jumper Configuration Options SP601 Evaluation Board References Appendix a References Default Jumper and Switch Settings Table B-1Default Jumper and Switch SettingsType/Function Default Appendix B Default Jumper and Switch Settings Vita 57.1 FMC Connections Table C-1VITA 57.1 FMC LPC ConnectionsLPC Pin FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn