Gpio Male Pin Header | Xilinx UG518 specs

Chapter 1: SP601 Evaluation Board

GPIO Male Pin Header

The SP601 provides a 2X6 GPIO male pin header supporting 3.3V power, GND and eight I/Os. Figure 1-26and Table 1-20describe the J13 GPIO Male Pin Header.

GPIO HDR0

GPIO HDR1

GPIO HDR2

GPIO HDR3

1/16W		R102	1/16W	200 5%	R100
1/16W	200 5%	R102	2	200 5%	1
2		1	1/16W	200 5%	R101
1/16W	200 5%	R103	2	200 5%	1
2		1

1 2

3 4

5 6

78

910

11 12

J13

R99	200	5%	1/16W				1/16W
1	200	5%	2	R98	200	5%	1/16W
1 R97	200	5%	1/16W	1			2
1 R97	200	5%	2	R96	200	5%	1/16W
				1			2

GPIO HDR4

GPIO HDR5

GPIO HDR6

GPIO HDR7

VCC3V3

UG518_24_070809

Figure 1-26:GPIO Male Pin Header Topology

Table 1-20:GPIO Header Pins

FPGA U1 Pin	Signal Name	J13 Pin

N17	GPIO_HDR0	1

M18	GPIO_HDR1	3

A3	GPIO_HDR2	5

L15	GPIO_HDR3	7

F15	GPIO_HDR4	2

B4	GPIO_HDR5	4

F13	GPIO_HDR6	6

P12	GPIO_HDR7	8

38	www.xilinx.com	SP601 Hardware User Guide
		UG518 (v1.1) August 19, 2009

Image 38

Xilinx UG518 manual Gpio Male Pin Header

Contents

SP601 Hardware User Guide UG518 v1.1 August 19, 2009 optional SP601 Hardware User Guide Revision History Date Version Revision SP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 Additional Resources Conventions Guide ContentsAbout This Guide Meaning or Use Example Online DocumentPreface About This Guide Additional Information SP601 Evaluation BoardOverview Features SP601 Evaluation Board Related Xilinx Documents Block DiagramRelated Xilinx Documents Detailed Description SP601 FeaturesFeature Detailed Description SP601 Features Cont’d NumberSpartan-6 XC6SLX16-2CSG324 Fpga 2I/O Voltage Rail of Fpga Banks MB DDR2 Component Memory Name Schematic Netname Memory U25DDR2 Component Memory Connections 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins SPI x4 Flash 6J12 SPI Flash Programming Header Schematic Netname Pin # Linear Flash BPI 8UCF Location Constraints for BPI Flash Connections FLASHA6 10UCF Location Constraints for BPI Flash Connections 10/100/1000 Tri-Speed Ethernet PHY 8PHY Configuration PinsSchematic Netname U3 M88E111 Pin Bit2 Bit1 Bit0 Schematic Netname U3 M88E111 SP601 Evaluation Board 9PHY Connections Cont’d USB-to-UART Bridge CP2103GM Connections IIC Bus 13IIC Bus Topology Clock Generation 14UCF Location Constraints for IIC Connections Vita 57.1 FMC-LPC Connector 16UCF Location Constraints for Oscillator Socket Connections 13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Reference Signal Name Color Label Description Status LEDs Suspend Mode I/O Fpga Awake LED and Suspend Jumper Fpga Init and Done LEDs Controlled LED Reference Signal Name Color Label Fpga Pin User I/O User DIP switch Reference Signal Name Color Label Fpga Pin Designator User Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O AC Adapter and 5V Input Power Jack/Switch Power ManagementFpgaprogb Pushbutton Switch Onboard Power Supplies Power Management 22Estimated Current Draw Rail Estimated Current a Configuration Options Jtag Configuration Configuration Options 32VITA 57.1 FMC Jtag Bypass Jumper SP601 Evaluation Board References Appendix a References Type/Function Default Default Jumper and Switch SettingsTable B-1Default Jumper and Switch Settings Appendix B Default Jumper and Switch Settings LPC Pin Vita 57.1 FMC ConnectionsTable C-1VITA 57.1 FMC LPC Connections FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn