Configuration Options | Xilinx UG518 specs

Configuration Options

J4

Bypass FMC LPC J1 = Jumper 1-2

Include FMC LPC J1 = Jumper 2-3

H - 1x3

1

FPGA_TD0

2

JTAG_TD0

3

FMC_TD0

UG518_32_081909

Figure 1-32:VITA 57.1 FMC JTAG Bypass Jumper

The JTAG chain can be used to program the FPGA and access the FPGA for hardware and software debug.

The JTAG connector (USB Mini-B J10) allows a host computer to download bitstreams to the FPGA using the iMPACT software tool, and also allows debug tools such as the ChipScope™ Pro Analyzer tool or a software debugger to access the FPGA.

The iMPACT software tool can also program the SPI x4 flash or the BPI flash via the USB J10 connection. iMPACT can download a temporary design to the FPGA through the JTAG. This provides a connection within the FPGA from the FPGA's JTAG port to the FPGA's SPI or BPI interface. Through the connection made by the temporary design in the FPGA, iMPACT can indirectly program the SPI flash or BPI flash from the JTAG USB J10 connector.

SP601 Hardware User Guide

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UG518 (v1.1) August 19, 2009

Image 43

Xilinx UG518 manual Configuration Options, 32VITA 57.1 FMC Jtag Bypass Jumper

Contents

UG518 v1.1 August 19, 2009 optional SP601 Hardware User Guide SP601 Hardware User Guide Date Version Revision Revision History SP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 About This Guide Guide ContentsAdditional Resources Conventions Preface About This Guide Online DocumentMeaning or Use Example Overview SP601 Evaluation BoardAdditional Information SP601 Evaluation Board Features Related Xilinx Documents Block DiagramRelated Xilinx Documents Feature SP601 FeaturesDetailed Description 2I/O Voltage Rail of Fpga Banks SP601 Features Cont’d NumberSpartan-6 XC6SLX16-2CSG324 Fpga Detailed Description MB DDR2 Component Memory 5DDR2 Component Memory Connections Schematic Netname Memory U2Name 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins 6J12 SPI Flash Programming Header SPI x4 Flash Pin # Schematic Netname 8UCF Location Constraints for BPI Flash Connections Linear Flash BPI FLASHA6 10UCF Location Constraints for BPI Flash Connections Bit2 Bit1 Bit0 8PHY Configuration PinsSchematic Netname U3 M88E111 Pin 10/100/1000 Tri-Speed Ethernet PHY SP601 Evaluation Board 9PHY Connections Cont’d Schematic Netname U3 M88E111 CP2103GM Connections USB-to-UART Bridge 13IIC Bus Topology IIC Bus 14UCF Location Constraints for IIC Connections Clock Generation 16UCF Location Constraints for Oscillator Socket Connections Vita 57.1 FMC-LPC Connector 13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Status LEDs Reference Signal Name Color Label Description Fpga Awake LED and Suspend Jumper Suspend Mode I/O Controlled LED Fpga Init and Done LEDs User I/O Reference Signal Name Color Label Fpga Pin Reference Signal Name Color Label Fpga Pin Designator User DIP switch User Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Onboard Power Supplies Power ManagementFpgaprogb Pushbutton Switch AC Adapter and 5V Input Power Jack/Switch 22Estimated Current Draw Rail Estimated Current a Power Management Jtag Configuration Configuration Options 32VITA 57.1 FMC Jtag Bypass Jumper Configuration Options SP601 Evaluation Board References Appendix a References Table B-1Default Jumper and Switch Settings Default Jumper and Switch SettingsType/Function Default Appendix B Default Jumper and Switch Settings Table C-1VITA 57.1 FMC LPC Connections Vita 57.1 FMC ConnectionsLPC Pin FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn