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Xilinx UG518 manual 5DDR2 Component Memory Connections, Schematic Netname Memory U2, Name

Models: UG518

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Detailed Description

Table 1-5shows the connections and pin numbers for the DDR2 Component Memory.

Table 1-5:DDR2 Component Memory Connections

	FPGA U1	Schematic Netname		Memory U2

			Pin Number		Name
			Pin Number		Name

	J7	DDR2_A0	M8		A0

	J6	DDR2_A1	M3		A1

	H5	DDR2_A2	M7		A2

	L7	DDR2_A3	N2		A3

	F3	DDR2_A4	N8		A4

	H4	DDR2_A5	N3		A5

	H3	DDR2_A6	N7		A6

	H6	DDR2_A7	P2		A7

	D2	DDR2_A8	P8		A8

	D1	DDR2_A9	P3		A9

	F4	DDR2_A10	M2		A10

	D3	DDR2_A11	P7		A11

	G6	DDR2_A12	R2		A12


	L2	DDR2_DQ0	G8		DQ0

	L1	DDR2_DQ1	G2		DQ1

	K2	DDR2_DQ2	H7		DQ2

	K1	DDR2_DQ3	H3		DQ3

	H2	DDR2_DQ4	H1		DQ4

	H1	DDR2_DQ5	H9		DQ5

	J3	DDR2_DQ6	F1		DQ6

	J1	DDR2_DQ7	F9		DQ7

	M3	DDR2_DQ8	C8		DQ8

	M1	DDR2_DQ9	C2		DQ9

	N2	DDR2_DQ10	D7		DQ10

	N1	DDR2_DQ11	D3		DQ11

	T2	DDR2_DQ12	D1		DQ12

	T1	DDR2_DQ13	D9		DQ13

	U2	DDR2_DQ14	B1		DQ14

	U1	DDR2_DQ15	B9		DQ15

SP601 Hardware User Guide

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UG518 (v1.1) August 19, 2009

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Xilinx UG518 manual 5DDR2 Component Memory Connections, Schematic Netname Memory U2, Name

Contents

UG518 v1.1 August 19, 2009 optional SP601 Hardware User GuideSP601 Hardware User Guide Date Version Revision Revision HistorySP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 Guide Contents About This GuideAdditional Resources Conventions Online Document Preface About This GuideMeaning or Use Example SP601 Evaluation Board OverviewAdditional Information SP601 Evaluation Board FeaturesBlock Diagram Related Xilinx DocumentsRelated Xilinx Documents SP601 Features FeatureDetailed Description 2I/O Voltage Rail of Fpga Banks SP601 Features Cont’d NumberSpartan-6 XC6SLX16-2CSG324 Fpga Detailed DescriptionMB DDR2 Component Memory Schematic Netname Memory U2 5DDR2 Component Memory ConnectionsName 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins 6J12 SPI Flash Programming Header SPI x4 FlashPin # Schematic Netname8UCF Location Constraints for BPI Flash Connections Linear Flash BPIFLASHA6 10UCF Location Constraints for BPI Flash Connections Bit2 Bit1 Bit0 8PHY Configuration PinsSchematic Netname U3 M88E111 Pin 10/100/1000 Tri-Speed Ethernet PHYSP601 Evaluation Board 9PHY Connections Cont’d Schematic Netname U3 M88E111CP2103GM Connections USB-to-UART Bridge13IIC Bus Topology IIC Bus14UCF Location Constraints for IIC Connections Clock Generation16UCF Location Constraints for Oscillator Socket Connections Vita 57.1 FMC-LPC Connector13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Status LEDs Reference Signal Name Color Label DescriptionFpga Awake LED and Suspend Jumper Suspend Mode I/OControlled LED Fpga Init and Done LEDsUser I/O Reference Signal Name Color Label Fpga PinReference Signal Name Color Label Fpga Pin Designator User DIP switchUser Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Onboard Power Supplies Power ManagementFpgaprogb Pushbutton Switch AC Adapter and 5V Input Power Jack/Switch22Estimated Current Draw Rail Estimated Current a Power ManagementJtag Configuration Configuration Options32VITA 57.1 FMC Jtag Bypass Jumper Configuration OptionsSP601 Evaluation Board References Appendix a References Default Jumper and Switch Settings Table B-1Default Jumper and Switch SettingsType/Function Default Appendix B Default Jumper and Switch Settings Vita 57.1 FMC Connections Table C-1VITA 57.1 FMC LPC ConnectionsLPC Pin FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn