FMCLA08N | Xilinx UG518 manual

Appendix C: VITA 57.1 FMC Connections

Table C-1:VITA 57.1 FMC LPC Connections (Cont’d)

J1 FMC	Schematic Netname	U1 FPGA		J1 FMC	Schematic Netname	U1 FPGA
LPC Pin	Schematic Netname	Pin		LPC Pin	Schematic Netname	Pin
LPC Pin		Pin		LPC Pin		Pin

G13	FMC_LA08_N	E11		H13	FMC_LA07_P	E7

G15	FMC_LA12_P	D6		H14	FMC_LA07_N	E8

G16	FMC_LA12_N	C6		H16	FMC_LA11_P	B12

G18	FMC_LA16_P	C7		H17	FMC_LA11_N	A12

G19	FMC_LA16_N	A7		H19	FMC_LA15_P	G9

G21	FMC_LA20_P	N7		H20	FMC_LA15_N	F9

G22	FMC_LA20_N	P8		H22	FMC_LA19_P	N6

G24	FMC_LA22_P	R7		H23	FMC_LA19_N	P7

G25	FMC_LA22_N	T7		H25	FMC_LA21_P	T4

G27	FMC_LA25_P	M11		H26	FMC_LA21_N	V4

G28	FMC_LA25_N	N11		H28	FMC_LA24_P	U8

G30	FMC_LA29_P	M8		H29	FMC_LA24_N	V8

G31	FMC_LA29_N	N8		H31	FMC_LA28_P	U11

G33	FMC_LA31_P	T6		H32	FMC_LA28_N	V11

G34	FMC_LA31_N	V6		H34	FMC_LA30_P	T12

G36	FMC_LA33_P	M10		H35	FMC_LA30_N	V12

G37	FMC_LA33_N	N9		H37	FMC_LA32_P	U15

				H38	FMC_LA32_N	V15

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		UG518 (v1.1) August 19, 2009

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Xilinx UG518 manual FMCLA08N

Contents

SP601 Hardware User Guide UG518 v1.1 August 19, 2009 optional SP601 Hardware User Guide Revision History Date Version Revision SP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 Additional Resources Conventions Guide ContentsAbout This Guide Meaning or Use Example Online DocumentPreface About This Guide Additional Information SP601 Evaluation BoardOverview Features SP601 Evaluation Board Related Xilinx Documents Block DiagramRelated Xilinx Documents Detailed Description SP601 FeaturesFeature Detailed Description SP601 Features Cont’d NumberSpartan-6 XC6SLX16-2CSG324 Fpga 2I/O Voltage Rail of Fpga Banks MB DDR2 Component Memory Name Schematic Netname Memory U25DDR2 Component Memory Connections 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins SPI x4 Flash 6J12 SPI Flash Programming Header Schematic Netname Pin # Linear Flash BPI 8UCF Location Constraints for BPI Flash Connections FLASHA6 10UCF Location Constraints for BPI Flash Connections 10/100/1000 Tri-Speed Ethernet PHY 8PHY Configuration PinsSchematic Netname U3 M88E111 Pin Bit2 Bit1 Bit0 Schematic Netname U3 M88E111 SP601 Evaluation Board 9PHY Connections Cont’d USB-to-UART Bridge CP2103GM Connections IIC Bus 13IIC Bus Topology Clock Generation 14UCF Location Constraints for IIC Connections Vita 57.1 FMC-LPC Connector 16UCF Location Constraints for Oscillator Socket Connections 13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Reference Signal Name Color Label Description Status LEDs Suspend Mode I/O Fpga Awake LED and Suspend Jumper Fpga Init and Done LEDs Controlled LED Reference Signal Name Color Label Fpga Pin User I/O User DIP switch Reference Signal Name Color Label Fpga Pin Designator User Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O AC Adapter and 5V Input Power Jack/Switch Power ManagementFpgaprogb Pushbutton Switch Onboard Power Supplies Power Management 22Estimated Current Draw Rail Estimated Current a Configuration Options Jtag Configuration Configuration Options 32VITA 57.1 FMC Jtag Bypass Jumper SP601 Evaluation Board References Appendix a References Type/Function Default Default Jumper and Switch SettingsTable B-1Default Jumper and Switch Settings Appendix B Default Jumper and Switch Settings LPC Pin Vita 57.1 FMC ConnectionsTable C-1VITA 57.1 FMC LPC Connections FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn