Online Document, Preface About This Guide | Xilinx UG518 specs

Preface: About This Guide

	Convention		Meaning or Use	Example

			Variables in a syntax statement
			for which you must supply	ngdbuild design_name
			values
	Italic font
	Italic font		References to other manuals	See the User Guide for more
			References to other manuals	information.
				information.

				If a wire is drawn so that it
			Emphasis in text	overlaps the pin of a symbol, the
				two nets are not connected.

	Dark Shading		Items that are not supported or	This feature is not supported
	Dark Shading		reserved	This feature is not supported
			reserved

			An optional entry or parameter.
	Square brackets	[ ]	However, in bus specifications,	ngdbuild [option_name]
	Square brackets	[ ]	such as bus[7:0], they are	design_name
			such as bus[7:0], they are	design_name
			required.

	Braces { }		A list of items from which you	lowpwr ={onoff}
	Braces { }		must choose one or more	lowpwr ={onoff}
			must choose one or more

	Vertical bar		Separates items in a list of	lowpwr ={onoff}
	Vertical bar		choices	lowpwr ={onoff}
			choices

	Angle brackets < >		User-defined variable or in code	<directory name>
	Angle brackets < >		samples	<directory name>
			samples

	Vertical ellipsis			IOB #1: Name = QOUT’
	Vertical ellipsis			IOB #2: Name = CLKIN’
	.		Repetitive material that has	IOB #2: Name = CLKIN’
	.		Repetitive material that has	.
	.		been omitted	.
	.		been omitted	.
	.			.
	.			.
				.

	Horizontal ellipsis . . .		Repetitive material that has	allow block block_name loc1
	Horizontal ellipsis . . .		been omitted	loc2 ... locn;
			been omitted	loc2 ... locn;

			The prefix ‘0x’ or the suffix ‘h’	A read of address 0x00112975
	Notations		indicate hexadecimal notation	returned 45524943h.

			An ‘_n’ means the signal is	usr_teof_n is active low.
			An ‘_n’ means the signal is
			active low
			active low

Online Document

The following conventions are used in this document:

	Convention	Meaning or Use	Example

			See the section “Additional
	Blue text	Cross-reference link to a location	Resources” for details.
	Blue text	in the current document	Refer to “Title Formats” in
		in the current document	Refer to “Title Formats” in
			Chapter 1 for details.

	Blue, underlined text	Hyperlink to a website (URL)	Go to http://www.xilinx.com
	Blue, underlined text	Hyperlink to a website (URL)	for the latest speed files.
			for the latest speed files.

8	www.xilinx.com	SP601 Hardware User Guide
		UG518 (v1.1) August 19, 2009

Image 8

Xilinx UG518 manual Online Document, Preface About This Guide, Meaning or Use Example

Contents

SP601 Hardware User Guide UG518 v1.1 August 19, 2009 optional SP601 Hardware User Guide Revision History Date Version Revision SP601 Hardware User Guide Table of Contents UG518 v1.1 August 19 Additional Resources Conventions Guide ContentsAbout This Guide Meaning or Use Example Online DocumentPreface About This Guide Additional Information SP601 Evaluation BoardOverview Features SP601 Evaluation Board Related Xilinx Documents Block DiagramRelated Xilinx Documents Detailed Description SP601 FeaturesFeature SP601 Features Cont’d Number Spartan-6 XC6SLX16-2CSG324 FpgaDetailed Description 2I/O Voltage Rail of Fpga Banks MB DDR2 Component Memory Name Schematic Netname Memory U25DDR2 Component Memory Connections 3UCF Location Constraints for DDR2 Sdram Address Inputs 4UCF Location Constraints for DDR2 Sdram Data I/O Pins SPI x4 Flash 6J12 SPI Flash Programming Header Schematic Netname Pin # Linear Flash BPI 8UCF Location Constraints for BPI Flash Connections FLASHA6 10UCF Location Constraints for BPI Flash Connections 8PHY Configuration Pins Schematic Netname U3 M88E111 Pin10/100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0 Schematic Netname U3 M88E111 SP601 Evaluation Board 9PHY Connections Cont’d USB-to-UART Bridge CP2103GM Connections IIC Bus 13IIC Bus Topology Clock Generation 14UCF Location Constraints for IIC Connections Vita 57.1 FMC-LPC Connector 16UCF Location Constraints for Oscillator Socket Connections 13 LPC Pinout 13 LPC Pinout Cont’d 18UCF Location Constraints for Vita 57.1 FMC-LPC Connections Reference Signal Name Color Label Description Status LEDs Suspend Mode I/O Fpga Awake LED and Suspend Jumper Fpga Init and Done LEDs Controlled LED Reference Signal Name Color Label Fpga Pin User I/O User DIP switch Reference Signal Name Color Label Fpga Pin Designator User Pushbutton Switches Gpio Male Pin Header 27UCF Location Constraints for User and General-Purpose I/O Power Management Fpgaprogb Pushbutton SwitchAC Adapter and 5V Input Power Jack/Switch Onboard Power Supplies Power Management 22Estimated Current Draw Rail Estimated Current a Configuration Options Jtag Configuration Configuration Options 32VITA 57.1 FMC Jtag Bypass Jumper SP601 Evaluation Board References Appendix a References Type/Function Default Default Jumper and Switch SettingsTable B-1Default Jumper and Switch Settings Appendix B Default Jumper and Switch Settings LPC Pin Vita 57.1 FMC ConnectionsTable C-1VITA 57.1 FMC LPC Connections FMCLA08N SP601 Master UCF Appendix D SP601 Master UCF SP601 Hardware User Guide NET Fpgacmpmosi NET Smaclkn