Analog Devices ADuC812 manual Op Amp Model Characteristics, Driving the A/D Converter

Page 15

ADuC812

Driving the A/D Converter

The ADC incorporates a successive approximation (SAR) archi- tecture involving a charge-sampled input stage. Figure 7 shows the equivalent circuit of the analog input section. Each ADC conversion is divided into two distinct phases as defined by the position of the switches in Figure 7. During the sampling phase (with SW1 and SW2 in the “track” position) a charge propor- tional to the voltage on the analog input is developed across the input sampling capacitor. During the conversion phase (with both switches in the “hold” position) the capacitor DAC is adjusted via internal SAR logic until the voltage on node A is zero indicating that the sampled charge on the input capacitor is balanced out by the charge being output by the capacitor DAC. The digital value finally contained in the SAR is then latched out as the result of the ADC conversion. Control of the SAR, and timing of acquisition and sampling modes, is handled automatically by built-in ADC control logic. Acquisition and conversion times are also fully configurable under user control.

AIN0

TEMPERATURE

ADuC812

 

SENSOR

 

AIN7

 

 

 

 

200

 

 

 

TRACK

 

 

 

SW1

 

CAPACITOR

 

 

 

 

HOLD

 

DAC

 

2pF

 

 

 

 

 

 

NODE A

 

 

 

SW2

 

 

TRACK

HOLD

COMPARATOR

 

 

 

AGND

 

 

 

Figure 7. Internal ADC Structure

Note that whenever a new input channel is selected, a residual charge from the 2 pF sampling capacitor places a transient on the newly selected input. The signal source must be capable of recovering from this transient before the sampling switches click into “hold” mode. Delays can be inserted in software (between channel selection and conversion request) to account for input stage settling, but a hardware solution will alleviate this burden from the software design task and will ultimately result in a cleaner system implementation. One hardware solution would be to choose a very fast settling op amp to drive each analog input. Such an op amp would need to fully settle from a small signal transient in less than 300 ns in order to guarantee adequate settling under all software configurations. A better solution, recom- mended for use with any amplifier, is shown in Figure 8.

Though at first glance the circuit in Figure 8 may look like a simple antialiasing filter, it actually serves no such purpose since its corner frequency is well above the Nyquist frequency, even at a 200 kHz sample rate. Though the R/C does helps to reject some incoming high-frequency noise, its primary function is to ensure that the transient demands of the ADC input stage are met. It

ADuC812

51

1 AIN0

0.01 F

Figure 8. Buffering Analog Inputs

does so by providing a capacitive bank from which the 2 pF sam- pling capacitor can draw its charge. Since the 0.01 ∝F capacitor in Figure 8 is more than 4096 times the size of the 2 pF sam- pling capacitor, its voltage will not change by more than one count (1/4096) of the 12-bit transfer function when the 2 pF charge from a previous channel is dumped onto it. A larger capacitor can be used if desired, but not a larger resistor (for reasons described below).

The Schottky diodes in Figure 8 may be necessary to limit the voltage applied to the analog input pin as per the data sheet absolute maximum ratings. They are not necessary if the op amp is powered from the same supply as the ADuC812 since in that case the op amp is unable to generate voltages above VDD or below ground. An op amp of some kind is necessary unless the signal source is very low impedance to begin with. DC leakage currents at the ADuC812’s analog inputs can cause measurable dc errors with external source impedances as little as 100 Ω or so. To ensure accurate ADC operation, keep the total source impedance at each analog input less than 61 Ω. The table below illustrates examples of how source impedance can affect dc accuracy.

Source

Error from 1 ∝A

Error from 10 ∝A

Impedance

Leakage Current

Leakage Current

61 Ω

61 ∝V = 0.1 LSB

610 ∝V = 1 LSB

610 Ω

610 ∝V = 1 LSB

6.1 mV = 10 LSB

Although Figure 8 shows the op amp operating at a gain of 1, you can of course configure it for any gain needed. Also, you can just as easily use an instrumentation amplifier in its place to condition differential signals. Use any modern amplifier that is capable of delivering the signal (0 to VREF) with minimal satura- tion. Some single-supply rail-to-rail op amps that are useful for this purpose include, but are certainly not limited to, the ones given in Table VI. Check Analog Devices literature (CD ROM data book, etc.) for details on these and other op amps and instrumentation amps.

Table VI. Some Single-Supply Op Amps

Op Amp Model

Characteristics

 

 

OP181/OP281/OP481

Micropower

OP191/OP291/OP491

I/O Good up to VDD, Low Cost

OP196/OP296/OP496

I/O to VDD, Micropower, Low Cost

OP183/OP283

High Gain-Bandwidth Product

OP162/OP262/OP462

High GBP, Micro Package

AD820/AD822/AD824

FET Input, Low Cost

AD823

FET Input, High GBP

 

 

Keep in mind that the ADC’s transfer function is 0 to VREF, and any signal range lost to amplifier saturation near ground will impact dynamic range. Though the op amps in Table VI are capable of delivering output signals very closely approaching

REV. B

–15–

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Contents General Description Functional Block DiagramADuC812 Table of ContentsDAC Channel Specifications DC ACCURACY11 ADC Channel Specifications DC ACCURACY3Calibrated Endpoint ERRORS5 Temperature SENSOR10Power Supply Monitor Characteristics DAC AC CharacteristicsFLASH/EE Memory Performance CHARACTERISTICS12 Watchdog Timer CharacteristicsIsource = 20 ∝A Power REQUIREMENTS14, 15Digital Outputs Isource = 80 ∝ATemperature Package Model Range Description Option PIN ConfigurationOrdering Guide Mnemonic Type Function Thus for a 12-bit converter, this is 74 dB ADC SpecificationsDAC Specifications TerminologyMemory Organization ARCHITECTURE, Main FeaturesBit Name Description Special Function Registers Default Value SFR Address SFR Notes Typical Operation ADC Circuit Information General Overview ADC Transfer FunctionADCCON1.1 T2C EFHAQ1 AQ0 #ADC ClksLocation Name Description CS3 CS2 CS1 CS0 CH#Bit Location Status Description Op Amp Model Characteristics Driving the A/D ConverterTable VI. Some Single-Supply Op Amps Configuring the ADC ADC DMA ModeVoltage Reference Connections Dmah and then by Dmap Where the ADC Results are to be written. This is done byExternal memory must be preconfigured. This consists DMAP. Dmal must be written to first, followed bySFR area Byte Program SequenceNonvolatile Flash Memory C6H EconB9H EadrlCommand Byte Command Mode RNG0 FDHMode RNG1Resistor String DAC Functional Equivalent Using the D/A ConverterSource and Sink Current Capability with Vref = VDD = 3 WDR1 C0HPRE2 PRE1 PRE0 PRE2Psmi DFHDCH CMPWcol F8HOOH IspiF7H SPR1SPR0 SPR1 SPR02C Control Register I2CCONCompatible ON-CHIP Peripherals Pin Alternate FunctionT2CON TMOD, TconTR0 TF1TR1 TF0TIMER/COUNTER 0 and 1 Operating Modes Mode 3 Two 8-Bit Timer/CountersMode 1 16-Bit Timer/Counter Rclk C8HTF2 EXF2CAP2 TR2 Mode Rclk or TclkOFF SM2 SM0SM1 SM0 SM1Baud rate in Mode 0 is fixed Smod CLKRCAP2H RCAP2L ET1 A8HEadc ET2Source Vector Address Source Priority DescriptionADuC812 Hardware Design Considerations Clock OscillatorExternal Memory Interface High it tracks the voltage on DVDD. These recommendations Down to 1.2 V or less. The timing diagram of illusADuC812-based system as well as during its normal power-on Level. The external POR circuit must be operationalCore NAs ⋅ Mclk + Normal ModeIdle Mode VDD = 5 VDD = 3System Grounding Schemes Grounding and Board Layout RecommendationsIn-Circuit Serial Download Access Other Hardware ConsiderationsEmbedded Serial Port Debugger ADSIM-Windows Simulator Quickstart Development SystemXTAL1 Rise Time XTAL1 Period 83.33 62.5 1000XTAL1 Width Low XTAL1 Width HighExternal Program Memory 12 MHz Variable Clock Parameter Min Max UnitExternal Data Memory Read Cycle External Data Memory Write Cycle Input Data Hold after Clock Output Data Setup to Clock 700 10t CKInput Data Setup to Clock 300 2t CK + Serial Port Clock Cycle Time 12t CKI2C-COMPATIBLE Interface Timing Parameter Min Max UnitParameter Min Typ Max Unit SPI Master Mode Timing Cpha =Data Output Setup before Sclock Edge 150 SPI Slave Mode Timing Cpha = SS to Sclock EdgeSS High after Sclock Edge Data Output Valid after SS Edge Lead Plastic Quad Flatpack Entire Data Sheet has been revisedOutline Dimensions Location Data Sheet changed from REV. a to REV. B
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