Analog Devices ADuC812 manual C8H, TF2, EXF2, Rclk, Tclk, EXEN2, TR2, CNT2, CAP2

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ADuC812

T2CON	Timer/Counter 2 Control Register
SFR Address	C8H
Power-On Default Value	00H
Bit Addressable	Yes

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

CNT2

CAP2

		Table XVIII. T2CON SFR Bit Designations

Bit	Name	Description

7	TF2	Timer 2 Overflow Flag.
		Set by hardware on a timer 2 overflow. TF2 will not be set when either RCLK or TCLK = 1.
		Cleared by user software.
6	EXF2	Timer 2 External Flag.
		Set by hardware when either a capture or reload is caused by a negative transition on T2EX and
		EXEN2 = 1.
		Cleared by user software.
5	RCLK	Receive Clock Enable Bit.
		Set by user to enable the serial port to use timer 2 overflow pulses for its receive clock in serial port
		Modes 1 and 3.
		Cleared by user to enable timer 1 overflow to be used for the receive clock.
4	TCLK	Transmit Clock Enable Bit.
		Set by user to enable the serial port to use timer 2 overflow pulses for its transmit clock in serial
		port Modes 1 and 3.
		Cleared by user to enable timer 1 overflow to be used for the transmit clock.
3	EXEN2	Timer 2 External Enable Flag.
		Set by user to enable a capture or reload to occur as a result of a negative transition on T2EX if
		Timer 2 is not being used to clock the serial port.
		Cleared by user for Timer 2 to ignore events at T2EX.
2	TR2	Timer 2 Start/Stop Control Bit.
		Set by user to start timer 2.
		Cleared by user to stop timer 2.
1	CNT2	Timer 2 Timer or Counter Function Select Bit.
		Set by user to select counter function (input from external T2 pin).
		Cleared by user to select timer function (input from on-chip core clock).
0	CAP2	Timer 2 Capture/Reload Select Bit.
		Set by user to enable captures on negative transitions at T2EX if EXEN2 = 1.
		Cleared by user to enable auto-reloads with Timer 2 overflows or negative transitions at T2EX
		when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is
		forced to autoreload on Timer 2 overflow.

Timer/Counter 2 Data Registers

Timer/Counter 2 also has two pairs of 8-bit data registers associated with it. These are used as both timer data registers and timer capture/reload registers.

TH2 and TL2

Timer 2, data high byte and low byte.

SFR Address = CDH, CCH respectively.

RCAP2H and RCAP2L

Timer 2, Capture/Reload byte and low byte.

SFR Address = CBH, CAH respectively.

REV. B

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Contents General Description Functional Block DiagramADuC812 Table of ContentsCalibrated Endpoint ERRORS5 ADC Channel Specifications DC ACCURACY3Temperature SENSOR10 DAC Channel Specifications DC ACCURACY11FLASH/EE Memory Performance CHARACTERISTICS12 DAC AC CharacteristicsWatchdog Timer Characteristics Power Supply Monitor CharacteristicsDigital Outputs Power REQUIREMENTS14, 15Isource = 80 ∝A Isource = 20 ∝ATemperature Package Model Range Description Option PIN ConfigurationOrdering Guide Mnemonic Type Function DAC Specifications ADC SpecificationsTerminology Thus for a 12-bit converter, this is 74 dBMemory Organization ARCHITECTURE, Main FeaturesBit Name Description Special Function Registers Default Value SFR Address SFR NotesGeneral Overview ADC Circuit InformationADC Transfer Function Typical OperationAQ1 EFHAQ0 #ADC Clks ADCCON1.1 T2CLocation Name Description CS3 CS2 CS1 CS0 CH#Bit Location Status Description Op Amp Model Characteristics Driving the A/D ConverterTable VI. Some Single-Supply Op Amps Configuring the ADC ADC DMA ModeVoltage Reference Connections External memory must be preconfigured. This consists Where the ADC Results are to be written. This is done byDMAP. Dmal must be written to first, followed by Dmah and then by DmapSFR area Byte Program SequenceNonvolatile Flash Memory B9H EconEadrl C6HCommand Byte Command Mode Mode FDHRNG1 RNG0Resistor String DAC Functional Equivalent Using the D/A ConverterSource and Sink Current Capability with Vref = VDD = 3 PRE2 C0HPRE1 PRE0 PRE2 WDR1DCH DFHCMP PsmiOOH F8HIspi WcolSPR0 SPR1SPR1 SPR0 F7H2C Control Register I2CCONCompatible ON-CHIP Peripherals Pin Alternate Function T2CON TMOD, TconTR1 TF1TF0 TR0TIMER/COUNTER 0 and 1 Operating Modes Mode 3 Two 8-Bit Timer/CountersMode 1 16-Bit Timer/Counter TF2 C8HEXF2 RclkCAP2 TR2 Mode Rclk or TclkOFF SM1 SM0SM0 SM1 SM2Baud rate in Mode 0 is fixed Smod CLKRCAP2H RCAP2L Eadc A8HET2 ET1Source Vector Address Source Priority DescriptionADuC812 Hardware Design Considerations Clock OscillatorExternal Memory Interface ADuC812-based system as well as during its normal power-on Down to 1.2 V or less. The timing diagram of illusLevel. The external POR circuit must be operational High it tracks the voltage on DVDD. These recommendationsIdle Mode Normal ModeVDD = 5 VDD = 3 Core NAs ⋅ Mclk +System Grounding Schemes Grounding and Board Layout RecommendationsIn-Circuit Serial Download Access Other Hardware ConsiderationsEmbedded Serial Port Debugger ADSIM-Windows Simulator Quickstart Development SystemXTAL1 Width Low XTAL1 Period 83.33 62.5 1000XTAL1 Width High XTAL1 Rise TimeExternal Program Memory 12 MHz Variable Clock Parameter Min Max UnitExternal Data Memory Read Cycle External Data Memory Write Cycle Input Data Setup to Clock 300 2t CK + Output Data Setup to Clock 700 10t CKSerial Port Clock Cycle Time 12t CK Input Data Hold after ClockI2C-COMPATIBLE Interface Timing Parameter Min Max UnitParameter Min Typ Max Unit SPI Master Mode Timing Cpha =Data Output Setup before Sclock Edge 150 SPI Slave Mode Timing Cpha = SS to Sclock EdgeSS High after Sclock Edge Data Output Valid after SS Edge Outline Dimensions Entire Data Sheet has been revisedLocation Data Sheet changed from REV. a to REV. B Lead Plastic Quad Flatpack