Analog Devices ADuC812 Temperature Package Model Range Description Option, PIN Configuration

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ADuC812

ABSOLUTE MAXIMUM RATINGS* (TA = 25°C unless otherwise noted)

PIN CONFIGURATION

AVDD to DVDD

. . . –0.3 V to +0.3 V

AGND to DGND

. . . –0.3 V to +0.3 V

DVDD to DGND, AVDD to AGND . . . .

. . . . . –0.3 V to +7 V

Digital Input Voltage to DGND

–0.3 V, DVDD + 0.3 V

Digital Output Voltage to DGND . . . .

–0.3 V, DVDD + 0.3 V

VREF to AGND

–0.3 V, AVDD + 0.3 V

Analog Inputs to AGND

–0.3 V, AVDD + 0.3 V

Operating Temperature Range Industrial (B Version)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . –40°C to +85°C

Storage Temperature Range

. . . –65°C to +150°C

Junction Temperature

. . . . . . . . . . . 150°C

θJA Thermal Impedance

. . . . . . . . . . 90°C/W

Lead Temperature, Soldering

. . . . . . . . . . . 215°C

Vapor Phase (60 sec)

Infrared (15 sec)

. . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

P1.0/ADC0/T2 1

P1.1/ADC1/T2EX 2

P1.2/ADC2 3

P1.3/ADC3 4

AVDD 5

AGND 6

CREF 7

VREF 8

DAC0 9

DAC1 10

P1.4/ADC4 11

P1.5/ADC5/SS 12

P1.6/ADC6 13

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

DV

DGND

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

ALE

PSEN

EA

 

 

 

 

DD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

52

51

50

49

48

47

46

45

44

43

42

41

40

PIN 1

IDENTIFIER

ADuC812

TOP VIEW

(Not to Scale)

14

15

16

17

18

19

20

21

22

23

24

25

26

P1.7/ADC7

RESET

P3.0/RxD

P3.1/TxD

P3.2/INT0

P3.3/INT1/MISO

DD

DGND

P3.4/T0

P3.5/T1/CONVST

P3.6/WR

P3.7/RD

SCLOCK

DV

39P2.7/A15/A23

38P2.6/A14/A22

37P2.5/A13/A21

36P2.4/A12/A20

35DGND

34DVDD

33XTAL2

32XTAL1

31P2.3/A11/A19

30P2.2/A10/A18

29P2.1/A9/A17

28P2.0/A8/A16

27SDATA/MOSI

ORDERING GUIDE

 

Temperature

Package

Package

Model

Range

Description

Option

 

 

 

 

ADuC812BS

–40°C to +85°C

52-Lead Plastic Quad Flatpack

S-52

Eval-ADuC812QS

 

QuickStart Development System

 

 

 

 

 

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADuC812 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–6–

REV. B

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Contents Functional Block Diagram General DescriptionTable of Contents ADuC812Temperature SENSOR10 ADC Channel Specifications DC ACCURACY3Calibrated Endpoint ERRORS5 DAC Channel Specifications DC ACCURACY11Watchdog Timer Characteristics DAC AC CharacteristicsFLASH/EE Memory Performance CHARACTERISTICS12 Power Supply Monitor CharacteristicsIsource = 80 ∝A Power REQUIREMENTS14, 15Digital Outputs Isource = 20 ∝ATemperature Package Model Range Description Option PIN ConfigurationOrdering Guide Mnemonic Type Function Terminology ADC SpecificationsDAC Specifications Thus for a 12-bit converter, this is 74 dBARCHITECTURE, Main Features Memory OrganizationBit Name Description Default Value SFR Address SFR Notes Special Function RegistersADC Transfer Function ADC Circuit InformationGeneral Overview Typical OperationAQ0 #ADC Clks EFHAQ1 ADCCON1.1 T2CLocation Name Description CS3 CS2 CS1 CS0 CH#Bit Location Status Description Op Amp Model Characteristics Driving the A/D ConverterTable VI. Some Single-Supply Op Amps Configuring the ADC ADC DMA ModeVoltage Reference Connections DMAP. Dmal must be written to first, followed by Where the ADC Results are to be written. This is done byExternal memory must be preconfigured. This consists Dmah and then by DmapSFR area Byte Program SequenceNonvolatile Flash Memory Eadrl EconB9H C6HCommand Byte Command Mode RNG1 FDHMode RNG0Using the D/A Converter Resistor String DAC Functional EquivalentSource and Sink Current Capability with Vref = VDD = 3 PRE1 PRE0 PRE2 C0HPRE2 WDR1CMP DFHDCH PsmiIspi F8HOOH WcolSPR1 SPR0 SPR1SPR0 F7HI2CCON 2C Control RegisterPin Alternate Function Compatible ON-CHIP PeripheralsTMOD, Tcon T2CONTF0 TF1TR1 TR0TIMER/COUNTER 0 and 1 Operating Modes Mode 3 Two 8-Bit Timer/CountersMode 1 16-Bit Timer/Counter EXF2 C8HTF2 RclkCAP2 TR2 Mode Rclk or TclkOFF SM0 SM1 SM0SM1 SM2Baud rate in Mode 0 is fixed Smod CLKRCAP2H RCAP2L ET2 A8HEadc ET1Source Priority Description Source Vector AddressADuC812 Hardware Design Considerations Clock OscillatorExternal Memory Interface Level. The external POR circuit must be operational Down to 1.2 V or less. The timing diagram of illusADuC812-based system as well as during its normal power-on High it tracks the voltage on DVDD. These recommendationsVDD = 5 VDD = 3 Normal ModeIdle Mode Core NAs ⋅ Mclk +Grounding and Board Layout Recommendations System Grounding SchemesIn-Circuit Serial Download Access Other Hardware ConsiderationsEmbedded Serial Port Debugger Quickstart Development System ADSIM-Windows SimulatorXTAL1 Width High XTAL1 Period 83.33 62.5 1000XTAL1 Width Low XTAL1 Rise Time12 MHz Variable Clock Parameter Min Max Unit External Program MemoryExternal Data Memory Read Cycle External Data Memory Write Cycle Serial Port Clock Cycle Time 12t CK Output Data Setup to Clock 700 10t CKInput Data Setup to Clock 300 2t CK + Input Data Hold after ClockParameter Min Max Unit I2C-COMPATIBLE Interface TimingSPI Master Mode Timing Cpha = Parameter Min Typ Max UnitData Output Setup before Sclock Edge 150 SPI Slave Mode Timing Cpha = SS to Sclock EdgeSS High after Sclock Edge Data Output Valid after SS Edge Location Data Sheet changed from REV. a to REV. B Entire Data Sheet has been revisedOutline Dimensions Lead Plastic Quad Flatpack
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