Analog Devices ADuC812 manual Entire Data Sheet has been revised, Outline Dimensions

Page 56

ADuC812

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

52-Lead Plastic Quad Flatpack

(S-52)

0.094 (2.39)

0.084 (2.13)

0.037 (0.95)

0.026 (0.65)

SEATING

PLANE

0.012 (0.30)

0.006 (0.15)

0.008 (0.20)

0.006 (0.15)

0.082 (2.09)

0.078 (1.97)

 

0.557 (14.15)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SQ

 

 

 

 

 

 

 

 

 

 

 

 

0.537 (13.65)

 

 

 

 

 

 

 

52

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

40

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

PIN 1

 

 

 

 

 

 

 

 

 

 

 

39

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TOP VIEW

 

 

 

0.398 (10.11)

SQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(PINS DOWN)

 

 

 

 

0.390 (9.91)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

27

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

26

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.025 (0.65)

0.014 (0.35)

 

 

 

 

 

 

 

 

 

 

 

BSC

 

0.010 (0.25)

 

 

 

 

 

 

 

 

C00208–0–10/01(B)

Revision History

Location

Page

Data Sheet changed from REV. A to REV. B.

Entire Data Sheet has been revised

All

PRINTED IN U.S.A.

–56–

REV. B

Page 55 Page 56
Image 56
Page 55 Page 56
Contents Functional Block Diagram General DescriptionTable of Contents ADuC812ADC Channel Specifications DC ACCURACY3 Calibrated Endpoint ERRORS5Temperature SENSOR10 DAC Channel Specifications DC ACCURACY11DAC AC Characteristics FLASH/EE Memory Performance CHARACTERISTICS12Watchdog Timer Characteristics Power Supply Monitor CharacteristicsPower REQUIREMENTS14, 15 Digital OutputsIsource = 80 ∝A Isource = 20 ∝AOrdering Guide Temperature Package Model Range Description OptionPIN Configuration Mnemonic Type Function ADC Specifications DAC SpecificationsTerminology Thus for a 12-bit converter, this is 74 dBARCHITECTURE, Main Features Memory OrganizationBit Name Description Default Value SFR Address SFR Notes Special Function RegistersADC Circuit Information General OverviewADC Transfer Function Typical OperationEFH AQ1AQ0 #ADC Clks ADCCON1.1 T2CBit Location Status Description Location Name DescriptionCS3 CS2 CS1 CS0 CH# Table VI. Some Single-Supply Op Amps Op Amp Model CharacteristicsDriving the A/D Converter Voltage Reference Connections Configuring the ADCADC DMA Mode Where the ADC Results are to be written. This is done by External memory must be preconfigured. This consistsDMAP. Dmal must be written to first, followed by Dmah and then by DmapNonvolatile Flash Memory SFR areaByte Program Sequence Econ B9HEadrl C6HCommand Byte Command Mode FDH ModeRNG1 RNG0Using the D/A Converter Resistor String DAC Functional EquivalentSource and Sink Current Capability with Vref = VDD = 3 C0H PRE2PRE1 PRE0 PRE2 WDR1DFH DCHCMP PsmiF8H OOHIspi WcolSPR1 SPR0SPR1 SPR0 F7HI2CCON 2C Control RegisterPin Alternate Function Compatible ON-CHIP PeripheralsTMOD, Tcon T2CONTF1 TR1TF0 TR0Mode 1 16-Bit Timer/Counter TIMER/COUNTER 0 and 1 Operating ModesMode 3 Two 8-Bit Timer/Counters C8H TF2EXF2 RclkOFF CAP2 TR2 ModeRclk or Tclk SM0 SM1SM0 SM1 SM2Baud rate in Mode 0 is fixed RCAP2H RCAP2L SmodCLK A8H EadcET2 ET1Source Priority Description Source Vector AddressExternal Memory Interface ADuC812 Hardware Design ConsiderationsClock Oscillator Down to 1.2 V or less. The timing diagram of illus ADuC812-based system as well as during its normal power-onLevel. The external POR circuit must be operational High it tracks the voltage on DVDD. These recommendationsNormal Mode Idle ModeVDD = 5 VDD = 3 Core NAs ⋅ Mclk +Grounding and Board Layout Recommendations System Grounding SchemesEmbedded Serial Port Debugger In-Circuit Serial Download AccessOther Hardware Considerations Quickstart Development System ADSIM-Windows SimulatorXTAL1 Period 83.33 62.5 1000 XTAL1 Width LowXTAL1 Width High XTAL1 Rise Time12 MHz Variable Clock Parameter Min Max Unit External Program MemoryExternal Data Memory Read Cycle External Data Memory Write Cycle Output Data Setup to Clock 700 10t CK Input Data Setup to Clock 300 2t CK +Serial Port Clock Cycle Time 12t CK Input Data Hold after ClockParameter Min Max Unit I2C-COMPATIBLE Interface TimingSPI Master Mode Timing Cpha = Parameter Min Typ Max UnitData Output Setup before Sclock Edge 150 SS High after Sclock Edge SPI Slave Mode Timing Cpha =SS to Sclock Edge Data Output Valid after SS Edge Entire Data Sheet has been revised Outline DimensionsLocation Data Sheet changed from REV. a to REV. B Lead Plastic Quad Flatpack
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