Analog Devices ADuC812 manual ADC Channel Specifications DC ACCURACY3, Calibrated Endpoint ERRORS5

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SPECIFICATIONS1, 2					ADuC812
SPECIFICATIONS1, 2	(AVDD = DVDD = 3.0 V or 5.0 V 10%, REFIN/REFOUT = 2.5 V Internal Reference, MCLKIN = 11.0592 MHz,
fSAMPLE = 200 kHz, DAC VOUT Load to AGND; RL = 2 k , CL = 100 pF. All specifications TA = TMIN to TMAX, unless otherwise noted.)
		ADuC812BS
Parameter		VDD = 5 V	VDD = 3 V	Unit	Test Conditions/Comments
ADC CHANNEL SPECIFICATIONS
DC ACCURACY3, 4
Resolution		12	12	Bits
Integral Nonlinearity		± 1/2	± 1/2	LSB typ	fSAMPLE = 100 kHz
		± 1.5		LSB max	fSAMPLE = 100 kHz
		± 1.5	± 1.5	LSB typ	fSAMPLE = 200 kHz
Differential Nonlinearity		± 1	± 1	LSB typ	fSAMPLE = 100 kHz. Guaranteed No
					Missing Codes at 5 V

CALIBRATED ENDPOINT ERRORS5, 6		± 5
Offset Error		± 5		LSB max
		± 1	± 2	LSB typ
Offset Error Match		1	1	LSB typ
Gain Error		± 6		LSB max
		± 1	± 2	LSB typ
Gain Error Match		1.5	1.5	LSB typ

USER SYSTEM CALIBRATION7		± 5	±5
Offset Calibration Range		± 5	±5	% of VREF typ
Gain Calibration Range		± 2.5	± 2.5	% of VREF typ
DYNAMIC PERFORMANCE					fIN = 10 kHz Sine Wave
Signal-to-Noise Ratio (SNR)8		70	70	dB typ	fSAMPLE = 100 kHz
Signal-to-Noise Ratio (SNR)8		70	70	dB typ
Total Harmonic Distortion (THD)		–78	–78	dB typ
Peak Harmonic or Spurious Noise		–78	–78	dB typ

ANALOG INPUT
Input Voltage Ranges		0 to VREF	0 to VREF	Volts
Leakage Current		± 10		∝A max
Input Capacitance9		± 1	± 1	∝A typ
Input Capacitance9		20	20	pF max
TEMPERATURE SENSOR10
Voltage Output at 25°C		600	600	mV typ	Can vary significantly (> ± 20%)
Voltage TC		–3.0	–3.0	mV/°C typ	from device to device

DAC CHANNEL SPECIFICATIONS
DC ACCURACY11
Resolution		12	12	Bits
Relative Accuracy		± 3	± 3	LSB typ
Differential Nonlinearity		± 0.5	± 1	LSB typ	Guaranteed 12-Bit Monotonic
Offset Error		± 60		mV max
		± 25	± 25	mV typ
Full-Scale Error		± 30		mV max
		± 10	± 10	mV typ
Full-Scale Mismatch		± 0.5	± 0.5	% typ	% of Full-Scale on DAC1

ANALOG OUTPUTS
Voltage Range_0		0 to VREF	0 to VREF	V typ
Voltage Range_1		0 to VDD	0 to VDD	V typ
Resistive Load		10	10	kΩ typ
Capacitive Load		100	100	pF typ
Output Impedance		0.5	0.5	Ω typ
ISINK		50	50	∝A typ

REV. B

–3–

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Contents General Description Functional Block DiagramADuC812 Table of ContentsDAC Channel Specifications DC ACCURACY11 ADC Channel Specifications DC ACCURACY3Calibrated Endpoint ERRORS5 Temperature SENSOR10Power Supply Monitor Characteristics DAC AC CharacteristicsFLASH/EE Memory Performance CHARACTERISTICS12 Watchdog Timer CharacteristicsIsource = 20 ∝A Power REQUIREMENTS14, 15Digital Outputs Isource = 80 ∝ATemperature Package Model Range Description Option PIN ConfigurationOrdering Guide Mnemonic Type Function Thus for a 12-bit converter, this is 74 dB ADC SpecificationsDAC Specifications TerminologyMemory Organization ARCHITECTURE, Main FeaturesBit Name Description Special Function Registers Default Value SFR Address SFR NotesTypical Operation ADC Circuit InformationGeneral Overview ADC Transfer FunctionADCCON1.1 T2C EFHAQ1 AQ0 #ADC ClksLocation Name Description CS3 CS2 CS1 CS0 CH#Bit Location Status Description Op Amp Model Characteristics Driving the A/D ConverterTable VI. Some Single-Supply Op Amps Configuring the ADC ADC DMA ModeVoltage Reference Connections Dmah and then by Dmap Where the ADC Results are to be written. This is done byExternal memory must be preconfigured. This consists DMAP. Dmal must be written to first, followed bySFR area Byte Program SequenceNonvolatile Flash Memory C6H EconB9H EadrlCommand Byte Command Mode RNG0 FDHMode RNG1Resistor String DAC Functional Equivalent Using the D/A ConverterSource and Sink Current Capability with Vref = VDD = 3 WDR1 C0HPRE2 PRE1 PRE0 PRE2Psmi DFHDCH CMPWcol F8HOOH IspiF7H SPR1SPR0 SPR1 SPR02C Control Register I2CCONCompatible ON-CHIP Peripherals Pin Alternate FunctionT2CON TMOD, TconTR0 TF1TR1 TF0TIMER/COUNTER 0 and 1 Operating Modes Mode 3 Two 8-Bit Timer/CountersMode 1 16-Bit Timer/Counter Rclk C8HTF2 EXF2CAP2 TR2 Mode Rclk or TclkOFF SM2 SM0SM1 SM0 SM1Baud rate in Mode 0 is fixed Smod CLKRCAP2H RCAP2L ET1 A8HEadc ET2Source Vector Address Source Priority DescriptionADuC812 Hardware Design Considerations Clock OscillatorExternal Memory Interface High it tracks the voltage on DVDD. These recommendations Down to 1.2 V or less. The timing diagram of illusADuC812-based system as well as during its normal power-on Level. The external POR circuit must be operationalCore NAs ⋅ Mclk + Normal ModeIdle Mode VDD = 5 VDD = 3System Grounding Schemes Grounding and Board Layout RecommendationsIn-Circuit Serial Download Access Other Hardware ConsiderationsEmbedded Serial Port Debugger ADSIM-Windows Simulator Quickstart Development SystemXTAL1 Rise Time XTAL1 Period 83.33 62.5 1000XTAL1 Width Low XTAL1 Width HighExternal Program Memory 12 MHz Variable Clock Parameter Min Max UnitExternal Data Memory Read Cycle External Data Memory Write Cycle Input Data Hold after Clock Output Data Setup to Clock 700 10t CKInput Data Setup to Clock 300 2t CK + Serial Port Clock Cycle Time 12t CKI2C-COMPATIBLE Interface Timing Parameter Min Max UnitParameter Min Typ Max Unit SPI Master Mode Timing Cpha =Data Output Setup before Sclock Edge 150 SPI Slave Mode Timing Cpha = SS to Sclock EdgeSS High after Sclock Edge Data Output Valid after SS Edge Lead Plastic Quad Flatpack Entire Data Sheet has been revisedOutline Dimensions Location Data Sheet changed from REV. a to REV. B