Analog Devices ADuC812 manual External Data Memory Read Cycle

ADuC812

		12 MHz		Variable Clock
Parameter		Min	Max	Min	Max	Unit	Figure
EXTERNAL DATA MEMORY READ CYCLE
tRLRH	RD Pulsewidth	400		6tCK – 100		ns	53
tAVLL	Address Valid after ALE Low	43		tCK – 40		ns	53
tLLAX	Address Hold after ALE Low	48		tCK – 35		ns	53
tRLDV	RD Low to Valid Data In		252		5tCK – 165	ns	53
tRHDX	Data and Address Hold after RD	0		0		ns	53
tRHDZ	Data Float after RD		97		2tCK –70	ns	53
tLLDV	ALE Low to Valid Data In		517		8tCK – 150	ns	53
tAVDV	Address to Valid Data In		585		9tCK – 165	ns	53
tLLWL	ALE Low to RD or WR Low	200	300	3tCK – 50	3tCK + 50	ns	53
tAVWL	Address Valid to RD or WR Low	203		4tCK – 130		ns	53
tRLAZ	RD Low to Address Float		0		0	ns	53
tWHLH	RD or WR High to ALE High	43	123	tCK – 40	6tCK – 100	ns	53

MCLK

ALE (O)

PSEN (O)

RD (O)

PORT 0 (I/O)

PORT 2 (O)

		tWHLH
	tLLDV
tLLWL		tRLRH
tAVWL
	tRLDV	tRHDZ
tLLAX
		tRHDX
tAVLL	tRLAZ
A0–A7 (OUT)		DATA (IN)
tAVDV
A16–A23		A8–A15

Figure 52. External Data Memory Read Cycle

–48– REV. B