Analog Devices ADuC812 SPI Slave Mode Timing Cpha =, SS to Sclock Edge, SS High after Sclock Edge

Page 54

ADuC812

Parameter		Min	Typ	Max	Unit	Figure

SPI SLAVE MODE TIMING (CPHA = 1)
tSS	SS to SCLOCK Edge	0			ns	59
tSL	SCLOCK Low Pulsewidth		330		ns	59
tSH	SCLOCK High Pulsewidth		330		ns	59
tDAV	Data Output Valid after SCLOCK Edge			50	ns	59
tDSU	Data Input Setup Time before SCLOCK Edge	100			ns	59
tDHD	Data Input Hold Time after SCLOCK Edge	100			ns	59
tDF	Data Output Fall Time		10	25	ns	59
tDR	Data Output Rise Time		10	25	ns	59
tSR	SCLOCK Rise Time		10	25	ns	59
tSF	SCLOCK Fall Time		10	25	ns	59
tSFS	SS High after SCLOCK Edge	0			ns	59

SCLOCK (CPOL=0)

SCLOCK (CPOL=1)

MISO

MOSI

tSS

tSH	tSL
tDAV	tDF
	MSB

MSB IN

tDR

BIT 6 – 1

tSFS

tSR tSF

LSB

LSB IN

tDSU tDHD

Figure 58. SPI Slave Mode Timing (CPHA = 1)

–54–

REV. B

Image 54

Contents Functional Block Diagram General DescriptionTable of Contents ADuC812Temperature SENSOR10 ADC Channel Specifications DC ACCURACY3Calibrated Endpoint ERRORS5 DAC Channel Specifications DC ACCURACY11Watchdog Timer Characteristics DAC AC CharacteristicsFLASH/EE Memory Performance CHARACTERISTICS12 Power Supply Monitor CharacteristicsIsource = 80 ∝A Power REQUIREMENTS14, 15Digital Outputs Isource = 20 ∝ATemperature Package Model Range Description Option PIN ConfigurationOrdering Guide Mnemonic Type Function Terminology ADC SpecificationsDAC Specifications Thus for a 12-bit converter, this is 74 dBARCHITECTURE, Main Features Memory OrganizationBit Name Description Default Value SFR Address SFR Notes Special Function RegistersADC Transfer Function ADC Circuit InformationGeneral Overview Typical OperationAQ0 #ADC Clks EFHAQ1 ADCCON1.1 T2CLocation Name Description CS3 CS2 CS1 CS0 CH#Bit Location Status Description Op Amp Model Characteristics Driving the A/D ConverterTable VI. Some Single-Supply Op Amps Configuring the ADC ADC DMA ModeVoltage Reference Connections DMAP. Dmal must be written to first, followed by Where the ADC Results are to be written. This is done byExternal memory must be preconfigured. This consists Dmah and then by DmapSFR area Byte Program SequenceNonvolatile Flash Memory Eadrl EconB9H C6HCommand Byte Command Mode RNG1 FDHMode RNG0Using the D/A Converter Resistor String DAC Functional EquivalentSource and Sink Current Capability with Vref = VDD = 3 PRE1 PRE0 PRE2 C0HPRE2 WDR1CMP DFHDCH PsmiIspi F8HOOH WcolSPR1 SPR0 SPR1SPR0 F7HI2CCON 2C Control RegisterPin Alternate Function Compatible ON-CHIP PeripheralsTMOD, Tcon T2CONTF0 TF1TR1 TR0TIMER/COUNTER 0 and 1 Operating Modes Mode 3 Two 8-Bit Timer/CountersMode 1 16-Bit Timer/Counter EXF2 C8HTF2 RclkCAP2 TR2 Mode Rclk or TclkOFF SM0 SM1 SM0SM1 SM2Baud rate in Mode 0 is fixed Smod CLKRCAP2H RCAP2L ET2 A8HEadc ET1Source Priority Description Source Vector AddressADuC812 Hardware Design Considerations Clock OscillatorExternal Memory Interface Level. The external POR circuit must be operational Down to 1.2 V or less. The timing diagram of illusADuC812-based system as well as during its normal power-on High it tracks the voltage on DVDD. These recommendationsVDD = 5 VDD = 3 Normal ModeIdle Mode Core NAs ⋅ Mclk +Grounding and Board Layout Recommendations System Grounding SchemesIn-Circuit Serial Download Access Other Hardware ConsiderationsEmbedded Serial Port Debugger Quickstart Development System ADSIM-Windows SimulatorXTAL1 Width High XTAL1 Period 83.33 62.5 1000XTAL1 Width Low XTAL1 Rise Time12 MHz Variable Clock Parameter Min Max Unit External Program MemoryExternal Data Memory Read Cycle External Data Memory Write Cycle Serial Port Clock Cycle Time 12t CK Output Data Setup to Clock 700 10t CKInput Data Setup to Clock 300 2t CK + Input Data Hold after ClockParameter Min Max Unit I2C-COMPATIBLE Interface TimingSPI Master Mode Timing Cpha = Parameter Min Typ Max UnitData Output Setup before Sclock Edge 150 SPI Slave Mode Timing Cpha = SS to Sclock EdgeSS High after Sclock Edge Data Output Valid after SS Edge Location Data Sheet changed from REV. a to REV. B Entire Data Sheet has been revisedOutline Dimensions Lead Plastic Quad Flatpack

ADuC812

Parameter

SPI SLAVE MODE TIMING (CPHA = 1)

SS to SCLOCK Edge

SCLOCK Fall Time

SS High after SCLOCK Edge

Figure 58. SPI Slave Mode Timing (CPHA = 1)