Analog Devices ADuC812 manual Using the D/A Converter, Resistor String DAC Functional Equivalent

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ADuC812

Using the D/A Converter

The on-chip D/A converter architecture consists of a resistor string DAC followed by an output buffer amplifier, the func- tional equivalent of which is illustrated in Figure 18. Details of the actual DAC architecture can be found in U.S. Patent Num- ber 5969657 (www.uspto.gov). Features of this architecture include inherent guaranteed monotonicity and excellent differ- ential linearity.

AVDD

 

ADuC812

 

 

VREF

R

 

 

R

OUTPUT

 

BUFFER

 

 

 

R

8

 

R

HIGH-Z

 

DISABLE

 

 

(FROM MCU)

 

R

 

Figure 18. Resistor String DAC Functional Equivalent

As illustrated in Figure 18, the reference source for each DAC is

user selectable in software. It can be either AVDD or VREF. In

0-to-AVDDmode, the DAC output transfer function spans from

0V to the voltage at the AVDD pin. In 0-to-VREFmode, the DAC output transfer function spans from 0 V to the internal

VREF or if an external reference is applied the voltage at the VREF pin. The DAC output buffer amplifier features a true rail-to-rail

output stage implementation. This means that, unloaded, each output is capable of swinging to within less than 100 mV of both AVDD and ground. Moreover, the DAC’s linearity specification (when driving a 10 kΩ resistive load to ground) is guaranteed through the full transfer function except codes 0 to 48, and, in 0-to-AVDDmode only, codes 3995 to 4095. Linearity degrada- tion near ground and VDD is caused by saturation of the output amplifier, and a general representation of its effects (neglecting offset and gain error) is illustrated in Figure 19. The dotted line in Figure 19 indicates the ideal transfer function, and the solid line represents what the transfer function might look like with endpoint nonlinearities due to saturation of the output amplifier. Note that Figure 19 represents a transfer function in 0-to-VDD

mode only. In 0-to-VREFmode (with VREF < VDD) the lower nonlinearity would be similar, but the upper portion of the

transfer function would follow the “ideal” line right to the end

(VREF in this case, not VDD), showing no signs of endpoint lin- earity errors.

VDD

 

VDD – 50mV

 

VDD – 100mV

 

100mV

 

50mV

 

0mV

 

000 HEX

FFF HEX

Figure 19. Endpoint Nonlinearities Due to Amplifier Saturation

The endpoint nonlinearities conceptually illustrated in Figure 19 get worse as a function of output loading. Most of the ADuC812’s data sheet specifications assume a 10 kΩ resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of Figure 19 become larger. With larger current demands, this can significantly limit output voltage swing. Figure 20 and Figure 21 illustrate this behavior. It should be noted that the upper trace in each of these figures is only valid for an

output range selection of 0-to-AVDD. In 0-to-VREFmode, DAC loading will not cause high-side voltage drops as long as the

reference voltage remains below the upper trace in the correspond-

ing figure. For example, if AVDD = 3 V and VREF = 2.5 V, the high-side voltage will not be affected by loads less than 5 mA.

But somewhere around 7 mA the upper curve in Figure 21 drops below 2.5 V (VREF) indicating that at these higher currents the output will not be capable of reaching VREF.

 

5

 

 

 

 

 

 

 

 

 

 

ITH 0FFF HEX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DAC LOADED W

 

 

 

 

– V

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOLTAGE

3

 

 

 

 

 

 

 

OUTPUT

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DAC LOADED W

ITH 0000 HEX

 

 

 

 

 

0

 

 

 

 

 

 

 

 

0

5

10

15

SOURCE/SINK CURRENT – mA

Figure 20. Source and Sink Current Capability with VREF = VDD = 5 V

–22–

REV. B

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Contents Functional Block Diagram General DescriptionTable of Contents ADuC812Temperature SENSOR10 ADC Channel Specifications DC ACCURACY3Calibrated Endpoint ERRORS5 DAC Channel Specifications DC ACCURACY11Watchdog Timer Characteristics DAC AC CharacteristicsFLASH/EE Memory Performance CHARACTERISTICS12 Power Supply Monitor CharacteristicsIsource = 80 ∝A Power REQUIREMENTS14, 15Digital Outputs Isource = 20 ∝APIN Configuration Temperature Package Model Range Description OptionOrdering Guide Mnemonic Type Function Terminology ADC SpecificationsDAC Specifications Thus for a 12-bit converter, this is 74 dBARCHITECTURE, Main Features Memory OrganizationBit Name Description Default Value SFR Address SFR Notes Special Function RegistersADC Transfer Function ADC Circuit InformationGeneral Overview Typical OperationAQ0 #ADC Clks EFHAQ1 ADCCON1.1 T2CCS3 CS2 CS1 CS0 CH# Location Name DescriptionBit Location Status Description Driving the A/D Converter Op Amp Model CharacteristicsTable VI. Some Single-Supply Op Amps ADC DMA Mode Configuring the ADCVoltage Reference Connections DMAP. Dmal must be written to first, followed by Where the ADC Results are to be written. This is done byExternal memory must be preconfigured. This consists Dmah and then by DmapByte Program Sequence SFR areaNonvolatile Flash Memory Eadrl EconB9H C6HCommand Byte Command Mode RNG1 FDHMode RNG0Using the D/A Converter Resistor String DAC Functional EquivalentSource and Sink Current Capability with Vref = VDD = 3 PRE1 PRE0 PRE2 C0HPRE2 WDR1CMP DFHDCH PsmiIspi F8HOOH WcolSPR1 SPR0 SPR1SPR0 F7HI2CCON 2C Control RegisterPin Alternate Function Compatible ON-CHIP PeripheralsTMOD, Tcon T2CONTF0 TF1TR1 TR0Mode 3 Two 8-Bit Timer/Counters TIMER/COUNTER 0 and 1 Operating ModesMode 1 16-Bit Timer/Counter EXF2 C8HTF2 RclkRclk or Tclk CAP2 TR2 ModeOFF SM0 SM1 SM0SM1 SM2Baud rate in Mode 0 is fixed CLK SmodRCAP2H RCAP2L ET2 A8HEadc ET1Source Priority Description Source Vector AddressClock Oscillator ADuC812 Hardware Design ConsiderationsExternal Memory Interface Level. The external POR circuit must be operational Down to 1.2 V or less. The timing diagram of illusADuC812-based system as well as during its normal power-on High it tracks the voltage on DVDD. These recommendationsVDD = 5 VDD = 3 Normal ModeIdle Mode Core NAs ⋅ Mclk +Grounding and Board Layout Recommendations System Grounding SchemesOther Hardware Considerations In-Circuit Serial Download AccessEmbedded Serial Port Debugger Quickstart Development System ADSIM-Windows SimulatorXTAL1 Width High XTAL1 Period 83.33 62.5 1000XTAL1 Width Low XTAL1 Rise Time12 MHz Variable Clock Parameter Min Max Unit External Program MemoryExternal Data Memory Read Cycle External Data Memory Write Cycle Serial Port Clock Cycle Time 12t CK Output Data Setup to Clock 700 10t CKInput Data Setup to Clock 300 2t CK + Input Data Hold after ClockParameter Min Max Unit I2C-COMPATIBLE Interface TimingSPI Master Mode Timing Cpha = Parameter Min Typ Max UnitData Output Setup before Sclock Edge 150 SS to Sclock Edge SPI Slave Mode Timing Cpha =SS High after Sclock Edge Data Output Valid after SS Edge Location Data Sheet changed from REV. a to REV. B Entire Data Sheet has been revisedOutline Dimensions Lead Plastic Quad Flatpack
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