Analog Devices ADuC812 manual Voltage Reference Connections, Configuring the ADC, ADC DMA Mode

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ADuC812

ground, no amplifier can deliver signals all the way to ground when powered by a single supply. Therefore, if a negative supply is available, you might consider using it to power the front-end amplifiers. If you do, however, be sure to include the Schottky diodes shown in Figure 8 (or at least the lower of the two diodes) to protect the analog input from undervoltage conditions. To summarize this section, use the circuit of Figure 8 to drive the analog input pins of the ADuC812.

Voltage Reference Connections

The on-chip 2.5 V bandgap voltage reference can be used as the reference source for the ADC and DACs. In order to ensure the accuracy of the voltage reference you must decouple both

VDD

EXTERNAL

VOLTAGE

REFERENCE

0.1 F

0.1 F

 

 

ADuC812

 

51

2.5V

 

 

BANDGAP

 

 

REFERENCE

 

BUFFER

VREF

8

 

 

 

CREF

7

 

 

 

the VREF pin and the CREF pin to ground with 0.1 ∝F ceramic chip capacitors as shown in Figure 9.

 

 

 

 

ADuC812

BUFFER

 

51

2.5V

 

 

BANDGAP

 

 

 

 

 

 

 

 

REFERENCE

 

 

 

BUFFER

 

 

VREF

8

 

 

 

 

 

0.1

F

 

 

 

 

 

CREF

7

 

0.1

F

 

 

 

 

 

Figure 9. Decoupling VREF and CREF

The internal voltage reference can also be tapped directly from the VREF pin, if desired, to drive external circuitry. However, a buffer must be used in this case to ensure that no current is

drawn from the VREF pin itself. The voltage on the CREF pin is that of an internal node within the buffer block, and its voltage

is critical to ADC and DAC accuracy. Do not connect anything to this pin except the capacitor, and be sure to keep trace- lengths short on the CREF capacitor, decoupling the node straight to the underlying ground plane.

The ADuC812 powers up with its internal voltage reference in the “off” state. The voltage reference turns on automatically whenever the ADC or either DAC gets enabled in software. Once enabled, the voltage reference requires approximately 65 ms to power up and settle to its specified value. Be sure that your software allows this time to elapse before initiating any conversions. If an external voltage reference is preferred, simply

connect it to the VREF pin as shown in Figure 10 to overdrive the internal reference.

To ensure accurate ADC operation, the voltage applied to VREF must be between 2.3 V and AVDD. In situations where analog input signals are proportional to the power supply (such as some strain-gage applications) it can be desirable to connect the VREF pin directly to AVDD. In such a configuration you must also connect the CREF pin directly to AVDD to circumvent internal buffer headroom limitations. This allows the ADC input trans- fer function to accurately span the full range 0 to AVDD.

Operation of the ADC or DACs with a reference voltage below

2.3V, however, may incur loss of accuracy eventually resulting in missing codes or nonmonotonicity. For that reason, do not use a reference voltage less than 2.3 V.

Figure 10. Using an External Voltage Reference

Configuring the ADC

The three SFRs (ADCCON1, ADCCON2, ADCCON3) con- figure the ADC. In nearly all cases, an acquisition time of 1 ADC clock (ADCCON1.2 = 0, ADCCON1.3 = 0) will provide plenty of time for the ADuC812 to acquire its signal before switching the internal track and hold amplifier in to hold mode. The only exception would be a high source impedance analog input, but these should be buffered first anyway since source impedances of greater than 610 Ω can cause dc errors as well.

The ADuC812’s successive approximation ADC is driven by a divided down version of the master clock. To ensure adequate ADC operation, this ADC clock must be between 400 kHz and 4 MHz, and optimum performance is obtained with ADC clock between 400 kHz and 3 MHz. Frequencies within this range can easily be achieved with master clock frequencies from 400 kHz to well above 16 MHz with the four ADC clock divide ratios to choose from. For example, with a 12 MHz master clock, set the ADC clock divide ratio to 4 (i.e., ADCCLK = MCLK/4 = 3 MHz) by setting the appropriate bits in ADCCON1 (ADCCON1.5 = 1, ADCCON1.4 = 0).

The total ADC conversion time is 15 ADC clocks, plus 1 ADC clock for synchronization, plus the selected acquisition time (1, 2, 3, or 4 ADC clocks). For the example above, with a 1 clock acquisition time, total conversion time is 17 ADC clocks (or 5.67 ∝s for a 3 MHz ADC clock).

In continuous conversion mode, a new conversion begins each time the previous one finishes. The sample rate is then simply the inverse of the total conversion time described above. In the example above, the continuous conversion mode sample rate would be 176.5 kHz.

ADC DMA Mode

The on-chip ADC has been designed to run at a maximum conversion speed of 5 ∝s (200 kHz sampling rate). When con- verting at this rate the ADuC812 micro has 5 ∝s to read the ADC result and store the result in memory for further post processing all within 5 ∝s otherwise the next ADC sample could be lost. In an interrupt driven routine the micro would also have to jump to the ADC Interrupt Service routine which will also increase the time required to store the ADC results. In applica- tions where the ADuC812 cannot sustain the interrupt rate, an ADC DMA mode is provided.

To enable DMA mode, Bit 6 in ADCCON2 (DMA) must be set. This allows the ADC results to be written directly to a 16 MByte external static memory SRAM (mapped into data memory space) without any interaction from the ADuC812

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Contents Functional Block Diagram General DescriptionTable of Contents ADuC812ADC Channel Specifications DC ACCURACY3 Calibrated Endpoint ERRORS5Temperature SENSOR10 DAC Channel Specifications DC ACCURACY11DAC AC Characteristics FLASH/EE Memory Performance CHARACTERISTICS12Watchdog Timer Characteristics Power Supply Monitor CharacteristicsPower REQUIREMENTS14, 15 Digital OutputsIsource = 80 ∝A Isource = 20 ∝APIN Configuration Temperature Package Model Range Description OptionOrdering Guide Mnemonic Type Function ADC Specifications DAC SpecificationsTerminology Thus for a 12-bit converter, this is 74 dBARCHITECTURE, Main Features Memory OrganizationBit Name Description Default Value SFR Address SFR Notes Special Function RegistersADC Circuit Information General OverviewADC Transfer Function Typical Operation EFH AQ1 AQ0 #ADC Clks ADCCON1.1 T2CCS3 CS2 CS1 CS0 CH# Location Name DescriptionBit Location Status Description Driving the A/D Converter Op Amp Model CharacteristicsTable VI. Some Single-Supply Op Amps ADC DMA Mode Configuring the ADCVoltage Reference Connections Where the ADC Results are to be written. This is done by External memory must be preconfigured. This consistsDMAP. Dmal must be written to first, followed by Dmah and then by DmapByte Program Sequence SFR areaNonvolatile Flash Memory Econ B9HEadrl C6HCommand Byte Command Mode FDH ModeRNG1 RNG0Using the D/A Converter Resistor String DAC Functional EquivalentSource and Sink Current Capability with Vref = VDD = 3 C0H PRE2PRE1 PRE0 PRE2 WDR1DFH DCHCMP PsmiF8H OOHIspi WcolSPR1 SPR0SPR1 SPR0 F7HI2CCON 2C Control RegisterPin Alternate Function Compatible ON-CHIP PeripheralsTMOD, Tcon T2CONTF1 TR1TF0 TR0Mode 3 Two 8-Bit Timer/Counters TIMER/COUNTER 0 and 1 Operating ModesMode 1 16-Bit Timer/Counter C8H TF2EXF2 RclkRclk or Tclk CAP2 TR2 ModeOFF SM0 SM1SM0 SM1 SM2Baud rate in Mode 0 is fixed CLK SmodRCAP2H RCAP2L A8H EadcET2 ET1Source Priority Description Source Vector AddressClock Oscillator ADuC812 Hardware Design ConsiderationsExternal Memory Interface Down to 1.2 V or less. The timing diagram of illus ADuC812-based system as well as during its normal power-onLevel. The external POR circuit must be operational High it tracks the voltage on DVDD. These recommendationsNormal Mode Idle ModeVDD = 5 VDD = 3 Core NAs ⋅ Mclk +Grounding and Board Layout Recommendations System Grounding SchemesOther Hardware Considerations In-Circuit Serial Download AccessEmbedded Serial Port Debugger Quickstart Development System ADSIM-Windows SimulatorXTAL1 Period 83.33 62.5 1000 XTAL1 Width LowXTAL1 Width High XTAL1 Rise Time12 MHz Variable Clock Parameter Min Max Unit External Program MemoryExternal Data Memory Read Cycle External Data Memory Write Cycle Output Data Setup to Clock 700 10t CK Input Data Setup to Clock 300 2t CK +Serial Port Clock Cycle Time 12t CK Input Data Hold after ClockParameter Min Max Unit I2C-COMPATIBLE Interface TimingSPI Master Mode Timing Cpha = Parameter Min Typ Max UnitData Output Setup before Sclock Edge 150 SS to Sclock Edge SPI Slave Mode Timing Cpha =SS High after Sclock Edge Data Output Valid after SS Edge Entire Data Sheet has been revised Outline DimensionsLocation Data Sheet changed from REV. a to REV. B Lead Plastic Quad Flatpack
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