Analog Devices ADuC812 manual Mnemonic Type Function

Page 7

ADuC812

 

 

PIN FUNCTION DESCRIPTIONS

 

 

 

Mnemonic

Type

Function

 

 

 

DVDD

P

Digital Positive Supply Voltage, 3 V or 5 V Nominal

AVDD

P

Analog Positive Supply Voltage, 3 V or 5 V Nominal

CREF

I

Decoupling Input for On-Chip Reference. Connect 0.1 ∝F between this pin and AGND.

VREF

I/O

Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the

 

 

reference source for the analog-to-digital converter. The nominal internal reference voltage is 2.5 V and this

 

 

appears at the pin. This pin can be overdriven by an external reference.

AGND

G

Analog Ground. Ground Reference point for the analog circuitry.

P1.0–P1.7

I

Port 1 is an 8-bit Input Port only. Unlike other Ports, Port 1 defaults to Analog Input Mode, to configure

 

 

any of these Port Pins as a digital input, write a “0” to the port bit. Port 1 pins are multifunction and share

 

 

the following functionality.

ADC0–ADC7

I

Analog Inputs. Eight single-ended analog inputs. Channel selection is via ADCCON2 SFR.

T2

I

Timer 2 Digital Input. Input to Timer/Counter 2. When Enabled, Counter 2 is incremented in response to

 

 

a 1 to 0 transition of the T2 input.

T2EX

I

Digital Input. Capture/Reload trigger for Counter 2 and also functions as an Up/Down control input for

 

 

Counter 2.

SSI Slave Select Input for the SPI Interface

SDATA

I/O

User Selectable, I2C-Compatible or SPI Data Input/Output Pin

SCLOCK

I/O

Serial Clock Pin for I2C-Compatible or SPI Serial Interface Clock

MOSI

I/O

SPI Master Output/Slave Input Data I/O Pin for SPI Interface

MISO

I/O

SPI Master Input/Slave Output Data I/O Pin for SPI Serial Interface

DAC0

O

Voltage Output from DAC0

DAC1

O

Voltage Output from DAC1

RESET

I

Digital Input. A high level on this pin for 24 master clock cycles while the oscillator is running resets the

 

 

device. External power-on reset (POR) circuity must be implemented to drive the RESET pin as described

 

 

in the Power-On Reset Operation section of this data sheet.

P3.0–P3.7

I/O

Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are

 

 

pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 3

 

 

pins being pulled externally low will source current because of the internal pull-up resistors. Port 3 pins also

 

 

contain various secondary functions which are described below.

RxD

I/O

Receiver Data Input (Asynchronous) or Data Input/Output (Synchronous) of Serial (UART) Port

TxD

O

Transmitter Data Output (Asynchronous) or Clock Output (Synchronous) of Serial (UART) Port

INT0

I

Interrupt 0, programmable edge or level triggered Interrupt input, which can be programmed to one of two

 

 

priority levels. This pin can also be used as a gate control input to Timer 0.

INT1

I

Interrupt 1, programmable edge or level triggered Interrupt input, which can be programmed to one of two

 

 

priority levels. This pin can also be used as a gate control input to Timer 1.

T0

I

Timer/Counter 0 Input

T1

I

Timer/Counter 1 Input

CONVST

I

Active low Convert Start Logic input for the ADC block when the external Convert start function is enabled.

 

 

A low-to-high transition on this input puts the track/hold into its hold mode and starts conversion.

WR

O

Write Control Signal, Logic Output. Latches the data byte from Port 0 into the external data memory.

RD

O

Read Control Signal, Logic Output. Enables the external data memory to Port 0.

XTAL2

O

Output of the Inverting Oscillator Amplifier

XTAL1

I

Input to the inverting oscillator amplifier and input to the internal clock generator circuits.

DGND

G

Digital Ground. Ground reference point for the digital circuitry.

P2.0–P2.7

I/O

Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are

(A8–A15)

 

pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 2

(A16–A23)

 

pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits

 

 

the high order address bytes during fetches from external program memory and middle and high order

 

 

address bytes during accesses to the external 24-bit external data memory space.

REV. B

–7–

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Contents General Description Functional Block DiagramADuC812 Table of ContentsDAC Channel Specifications DC ACCURACY11 ADC Channel Specifications DC ACCURACY3Calibrated Endpoint ERRORS5 Temperature SENSOR10Power Supply Monitor Characteristics DAC AC CharacteristicsFLASH/EE Memory Performance CHARACTERISTICS12 Watchdog Timer CharacteristicsIsource = 20 ∝A Power REQUIREMENTS14, 15Digital Outputs Isource = 80 ∝APIN Configuration Temperature Package Model Range Description OptionOrdering Guide Mnemonic Type Function Thus for a 12-bit converter, this is 74 dB ADC SpecificationsDAC Specifications TerminologyMemory Organization ARCHITECTURE, Main FeaturesBit Name Description Special Function Registers Default Value SFR Address SFR NotesTypical Operation ADC Circuit InformationGeneral Overview ADC Transfer FunctionADCCON1.1 T2C EFHAQ1 AQ0 #ADC ClksCS3 CS2 CS1 CS0 CH# Location Name DescriptionBit Location Status Description Driving the A/D Converter Op Amp Model CharacteristicsTable VI. Some Single-Supply Op Amps ADC DMA Mode Configuring the ADCVoltage Reference Connections Dmah and then by Dmap Where the ADC Results are to be written. This is done byExternal memory must be preconfigured. This consists DMAP. Dmal must be written to first, followed byByte Program Sequence SFR areaNonvolatile Flash Memory C6H EconB9H EadrlCommand Byte Command Mode RNG0 FDHMode RNG1Resistor String DAC Functional Equivalent Using the D/A ConverterSource and Sink Current Capability with Vref = VDD = 3 WDR1 C0HPRE2 PRE1 PRE0 PRE2Psmi DFHDCH CMPWcol F8HOOH IspiF7H SPR1SPR0 SPR1 SPR02C Control Register I2CCONCompatible ON-CHIP Peripherals Pin Alternate FunctionT2CON TMOD, TconTR0 TF1TR1 TF0Mode 3 Two 8-Bit Timer/Counters TIMER/COUNTER 0 and 1 Operating ModesMode 1 16-Bit Timer/Counter Rclk C8HTF2 EXF2Rclk or Tclk CAP2 TR2 ModeOFF SM2 SM0SM1 SM0 SM1Baud rate in Mode 0 is fixed CLK SmodRCAP2H RCAP2L ET1 A8HEadc ET2Source Vector Address Source Priority DescriptionClock Oscillator ADuC812 Hardware Design ConsiderationsExternal Memory Interface High it tracks the voltage on DVDD. These recommendations Down to 1.2 V or less. The timing diagram of illusADuC812-based system as well as during its normal power-on Level. The external POR circuit must be operationalCore NAs ⋅ Mclk + Normal ModeIdle Mode VDD = 5 VDD = 3System Grounding Schemes Grounding and Board Layout RecommendationsOther Hardware Considerations In-Circuit Serial Download AccessEmbedded Serial Port Debugger ADSIM-Windows Simulator Quickstart Development SystemXTAL1 Rise Time XTAL1 Period 83.33 62.5 1000XTAL1 Width Low XTAL1 Width HighExternal Program Memory 12 MHz Variable Clock Parameter Min Max UnitExternal Data Memory Read Cycle External Data Memory Write Cycle Input Data Hold after Clock Output Data Setup to Clock 700 10t CKInput Data Setup to Clock 300 2t CK + Serial Port Clock Cycle Time 12t CKI2C-COMPATIBLE Interface Timing Parameter Min Max UnitParameter Min Typ Max Unit SPI Master Mode Timing Cpha =Data Output Setup before Sclock Edge 150 SS to Sclock Edge SPI Slave Mode Timing Cpha =SS High after Sclock Edge Data Output Valid after SS Edge Lead Plastic Quad Flatpack Entire Data Sheet has been revisedOutline Dimensions Location Data Sheet changed from REV. a to REV. B
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