Analog Devices ADuC812 Serial Port Clock Cycle Time 12t CK, Output Data Setup to Clock 700 10t CK

ADuC812

		12 MHz	Variable Clock
Parameter		Min Typ Max	Min	Typ	Max	Unit	Figure
UART TIMING (Shift Register Mode)
tXLXL	Serial Port Clock Cycle Time	1.0		12tCK		∝s	55
tQVXH	Output Data Setup to Clock	700	10tCK – 133			ns	55
tDVXH	Input Data Setup to Clock	300	2tCK + 133			ns	55
tXHDX	Input Data Hold after Clock	0	0			ns	55
tXHQX	Output Data Hold after Clock	50	2tCK – 117			ns	55

ALE (O)

tXLXL

TxD	0	1	6	7
(OUTPUT CLOCK)
		tQVXH		SET RI
				OR
			tXHQX	SET TI
RxD	MSB	BIT6	BIT1	LSB
(OUTPUT DATA)
		tDVXH	tXHDX
RxD	MSB	BIT6	BIT1	LSB
(INPUT DATA)

Figure 54. UART Timing in Shift Register Mode

–50– REV. B