Analog Devices ADuC812 manual Dfh, Dch, Cmp, Psmi, TP2 TP1 TP0, Psf, Psmen

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ADuC812

POWER SUPPLY MONITOR

As its name suggests, the Power Supply Monitor, once enabled, monitors both supplies (AVDD and DVDD) on the ADuC812. It will indicate when either power supply drops below one of five user-selectable voltage trip points from 2.63 V to 4.63 V. For correct operation of the Power Supply Monitor function, AVDD must be equal to or greater than 2.7 V. The Power Supply Monitor function is controlled via the PSMCON SFR. If enabled via the IE2 SFR, the Power Supply Monitor will interrupt

PSMCON

Power Supply Monitor

 

Control Register

SFR Address

DFH

Power-On Default Value

DCH

Bit Addressable

No

the core using the PSMI bit in the PSMCON SFR. This bit will not be cleared until the failing power supply has returned above the trip point for at least 256 ms. This is to ensure that the power supply has fully settled before the bit is cleared. This monitor function allows the user to save working registers to avoid possible data loss due to the low supply condition, and also ensures that normal code execution will not resume until a safe supply level has been well established. The supply monitor is also protected against spurious glitches triggering the interrupt circuit.

—

CMP

PSMI

TP2

TP1

TP0

PSF

PSMEN

 

 

 

Table X. PSMCON SFR Bit Designations

 

 

 

 

 

Bit

Name

Description

 

 

 

 

 

 

 

7

—

Not Used.

 

 

6

CMP

AVDD and DVDD Comparator Bit.

 

 

 

This is a read-only bit and directly reflects the state of the AVDD and DVDD comparators.

 

 

Read “1” indicates that both AVDD and DVDD supply are above its selected trip point.

 

 

Read “0” indicates that either AVDD or DVDD supply are below its selected trip point.

5

PSMI

Power Supply Monitor Interrupt Bit.

 

 

This bit will be set high by the MicroConverter if CMP is low, indicating low analog

 

 

or digital supply. The PSMI bit can be used to interrupt the processor. Once CMPD

 

 

and/or CMP return (and remain) high, a 256 ms counter is started. When this counter

 

 

times out, the PSMI interrupt is cleared. PSMI can also be written by the user. How

 

 

ever, if either comparator output is low, it is not possible for the user to clear PSMI.

4

TP2

VDD Trip Point Selection Bits.

 

3

TP1

 

 

 

 

2

TP0

These bits select the AVDD and DVDD trip-point voltage as follows:

 

 

TP2

TP1

TP0

Selected DVDD Trip Point (V)

 

 

0

0

0

4.63

 

 

0

0

1

4.37

 

 

0

1

0

3.08

 

 

0

1

1

2.93

 

 

1

0

0

2.63

1

PSF

AVDD/DVDD fault indicator

 

 

 

Read “1” indicates that the AVDD supply caused the fault condition.

 

 

Read “0” indicates that the DVDD supply caused the fault condition.

0

PSMEN

Power Supply Monitor Enable Bit.

 

 

 

Set to “1” by the user to enable the Power Supply Monitor Circuit.

 

 

Cleared to “0” by the user to disable the Power Supply Monitor Circuit.

 

 

 

 

 

 

Example

To configure the PSM for a trippoint of 4.37 V, the following code would be used

MOV

PSMCON,#005h

;enable PSM with

 

 

;4.37V threshold

SETB

EA

;enable

interrupts

MOV

IE2,#002h

;enable

PSM

 

 

;interrupt

If the supply voltage falls below this level, the PC would vector to the ISR.

ORG

0043h

;PSM ISR

CHECK:MOV

A,PSMCON

;PSMCON.5 is the

 

 

;PSM interrupt

 

 

;bit..

JB

ACC.5,CHECK

;..it is cleared

 

 

;only when Vdd

 

 

;has remained

 

 

;above the trip

 

 

;point for 256ms

 

 

;or more.

RETI

; return only when "all's well"

REV. B

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Contents General Description Functional Block DiagramADuC812 Table of ContentsCalibrated Endpoint ERRORS5 ADC Channel Specifications DC ACCURACY3Temperature SENSOR10 DAC Channel Specifications DC ACCURACY11FLASH/EE Memory Performance CHARACTERISTICS12 DAC AC CharacteristicsWatchdog Timer Characteristics Power Supply Monitor CharacteristicsDigital Outputs Power REQUIREMENTS14, 15Isource = 80 ∝A Isource = 20 ∝APIN Configuration Temperature Package Model Range Description OptionOrdering Guide Mnemonic Type Function DAC Specifications ADC SpecificationsTerminology Thus for a 12-bit converter, this is 74 dBMemory Organization ARCHITECTURE, Main FeaturesBit Name Description Special Function Registers Default Value SFR Address SFR NotesGeneral Overview ADC Circuit InformationADC Transfer Function Typical OperationAQ1 EFHAQ0 #ADC Clks ADCCON1.1 T2CCS3 CS2 CS1 CS0 CH# Location Name DescriptionBit Location Status Description Driving the A/D Converter Op Amp Model CharacteristicsTable VI. Some Single-Supply Op Amps ADC DMA Mode Configuring the ADCVoltage Reference Connections External memory must be preconfigured. This consists Where the ADC Results are to be written. This is done byDMAP. Dmal must be written to first, followed by Dmah and then by DmapByte Program Sequence SFR areaNonvolatile Flash Memory B9H EconEadrl C6HCommand Byte Command Mode Mode FDHRNG1 RNG0Resistor String DAC Functional Equivalent Using the D/A ConverterSource and Sink Current Capability with Vref = VDD = 3 PRE2 C0HPRE1 PRE0 PRE2 WDR1DCH DFHCMP PsmiOOH F8HIspi WcolSPR0 SPR1SPR1 SPR0 F7H2C Control Register I2CCONCompatible ON-CHIP Peripherals Pin Alternate FunctionT2CON TMOD, TconTR1 TF1TF0 TR0Mode 3 Two 8-Bit Timer/Counters TIMER/COUNTER 0 and 1 Operating ModesMode 1 16-Bit Timer/Counter TF2 C8HEXF2 RclkRclk or Tclk CAP2 TR2 ModeOFF SM1 SM0SM0 SM1 SM2Baud rate in Mode 0 is fixed CLK SmodRCAP2H RCAP2L Eadc A8HET2 ET1Source Vector Address Source Priority DescriptionClock Oscillator ADuC812 Hardware Design ConsiderationsExternal Memory Interface ADuC812-based system as well as during its normal power-on Down to 1.2 V or less. The timing diagram of illusLevel. The external POR circuit must be operational High it tracks the voltage on DVDD. These recommendationsIdle Mode Normal ModeVDD = 5 VDD = 3 Core NAs ⋅ Mclk +System Grounding Schemes Grounding and Board Layout RecommendationsOther Hardware Considerations In-Circuit Serial Download AccessEmbedded Serial Port Debugger ADSIM-Windows Simulator Quickstart Development SystemXTAL1 Width Low XTAL1 Period 83.33 62.5 1000XTAL1 Width High XTAL1 Rise TimeExternal Program Memory 12 MHz Variable Clock Parameter Min Max UnitExternal Data Memory Read Cycle External Data Memory Write Cycle Input Data Setup to Clock 300 2t CK + Output Data Setup to Clock 700 10t CKSerial Port Clock Cycle Time 12t CK Input Data Hold after ClockI2C-COMPATIBLE Interface Timing Parameter Min Max UnitParameter Min Typ Max Unit SPI Master Mode Timing Cpha =Data Output Setup before Sclock Edge 150 SS to Sclock Edge SPI Slave Mode Timing Cpha =SS High after Sclock Edge Data Output Valid after SS Edge Outline Dimensions Entire Data Sheet has been revisedLocation Data Sheet changed from REV. a to REV. B Lead Plastic Quad Flatpack
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