Analog Devices ADuC812 manual SM0 SM1, SM2, Ren, TB8, RB8

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ADuC812

UART SERIAL INTERFACE

The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can com- mence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, the first byte will be lost. The physical inter- face to the serial data network is via Pins RXD(P3.0) and

SCON

UART Serial Port Control

 

Register

SFR Address

98H

Power-On Default Value

00H

Bit Addressable

Yes

TXD(P3.1) while the SFR interface to the UART is comprised of SBUF and SCON, as described below.

SBUF

The serial port receive and transmit registers are both accessed through the SBUF SFR (SFR address = 99 hex). Writing to SBUF loads the transmit register and reading SBUF accesses a physically separate receive register.

SM0

SM1

SM2

REN

TB8

RB8

TI

RI

Table XX. SCON SFR Bit Designations

Bit

Name

Description

 

 

 

 

7

SM0

UART Serial Mode Select Bits.

6

SM1

These bits select the Serial Port operating mode as follows:

 

 

SM0

SM1

Selected Operating Mode

 

 

0

0

Mode 0: Shift Register, fixed baud rate (Core_Clk/2)

 

 

0

1

Mode 1: 8-bit UART, variable baud rate

 

 

1

0

Mode 2: 9-bit UART, fixed baud rate (Core_Clk/64) or

 

 

 

 

(Core_Clk/32)

 

 

1

1

Mode 3: 9-bit UART, variable baud rate

5

SM2

Multiprocessor Communication Enable Bit.

 

 

Enables multiprocessor communication in Modes 2 and 3. In Mode 0, SM2 should be cleared.

 

 

In Mode 1, if SM2 is set, RI will not be activated if a valid stop bit was not received. If SM2 is

 

 

cleared, RI will be set as soon as the byte of data has been received. In Modes 2 or 3, if SM2 is

 

 

set, RI will not be activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI will

 

 

be set as soon as the byte of data has been received.

4

REN

Serial Port Receive Enable Bit.

 

 

Set by user software to enable serial port reception.

 

 

Cleared by user software to disable serial port reception.

3

TB8

Serial Port Transmit (Bit 9).

 

 

The data loaded into TB8 will be the ninth data bit that will be transmitted in Modes 2 and 3.

2

RB8

Serial port Receiver Bit 9.

 

 

The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1 the stop bit is

 

 

latched into RB8.

 

1

TI

Serial Port Transmit Interrupt Flag.

 

 

Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in

 

 

Modes 1, 2, and 3. TI must be cleared by user software.

0

RI

Serial Port Receive Interrupt Flag.

 

 

Set by hardware at the end of the eighth bit in mode 0, or halfway through the stop bit in

 

 

Modes 1, 2, and 3. RI must be cleared by software.

 

 

 

 

 

REV. B

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Contents General Description Functional Block DiagramADuC812 Table of ContentsDAC Channel Specifications DC ACCURACY11 ADC Channel Specifications DC ACCURACY3Calibrated Endpoint ERRORS5 Temperature SENSOR10Power Supply Monitor Characteristics DAC AC CharacteristicsFLASH/EE Memory Performance CHARACTERISTICS12 Watchdog Timer CharacteristicsIsource = 20 ∝A Power REQUIREMENTS14, 15Digital Outputs Isource = 80 ∝AOrdering Guide Temperature Package Model Range Description OptionPIN Configuration Mnemonic Type Function Thus for a 12-bit converter, this is 74 dB ADC SpecificationsDAC Specifications TerminologyMemory Organization ARCHITECTURE, Main FeaturesBit Name Description Special Function Registers Default Value SFR Address SFR NotesTypical Operation ADC Circuit InformationGeneral Overview ADC Transfer FunctionADCCON1.1 T2C EFHAQ1 AQ0 #ADC ClksBit Location Status Description Location Name DescriptionCS3 CS2 CS1 CS0 CH# Table VI. Some Single-Supply Op Amps Op Amp Model CharacteristicsDriving the A/D Converter Voltage Reference Connections Configuring the ADCADC DMA Mode Dmah and then by Dmap Where the ADC Results are to be written. This is done byExternal memory must be preconfigured. This consists DMAP. Dmal must be written to first, followed byNonvolatile Flash Memory SFR areaByte Program Sequence C6H EconB9H EadrlCommand Byte Command Mode RNG0 FDHMode RNG1Resistor String DAC Functional Equivalent Using the D/A ConverterSource and Sink Current Capability with Vref = VDD = 3 WDR1 C0HPRE2 PRE1 PRE0 PRE2Psmi DFHDCH CMPWcol F8HOOH IspiF7H SPR1SPR0 SPR1 SPR02C Control Register I2CCONCompatible ON-CHIP Peripherals Pin Alternate FunctionT2CON TMOD, TconTR0 TF1TR1 TF0Mode 1 16-Bit Timer/Counter TIMER/COUNTER 0 and 1 Operating ModesMode 3 Two 8-Bit Timer/Counters Rclk C8HTF2 EXF2OFF CAP2 TR2 ModeRclk or Tclk SM2 SM0SM1 SM0 SM1Baud rate in Mode 0 is fixed RCAP2H RCAP2L SmodCLK ET1 A8HEadc ET2Source Vector Address Source Priority DescriptionExternal Memory Interface ADuC812 Hardware Design ConsiderationsClock Oscillator High it tracks the voltage on DVDD. These recommendations Down to 1.2 V or less. The timing diagram of illusADuC812-based system as well as during its normal power-on Level. The external POR circuit must be operationalCore NAs ⋅ Mclk + Normal ModeIdle Mode VDD = 5 VDD = 3System Grounding Schemes Grounding and Board Layout RecommendationsEmbedded Serial Port Debugger In-Circuit Serial Download AccessOther Hardware Considerations ADSIM-Windows Simulator Quickstart Development SystemXTAL1 Rise Time XTAL1 Period 83.33 62.5 1000XTAL1 Width Low XTAL1 Width HighExternal Program Memory 12 MHz Variable Clock Parameter Min Max UnitExternal Data Memory Read Cycle External Data Memory Write Cycle Input Data Hold after Clock Output Data Setup to Clock 700 10t CKInput Data Setup to Clock 300 2t CK + Serial Port Clock Cycle Time 12t CKI2C-COMPATIBLE Interface Timing Parameter Min Max UnitParameter Min Typ Max Unit SPI Master Mode Timing Cpha =Data Output Setup before Sclock Edge 150 SS High after Sclock Edge SPI Slave Mode Timing Cpha =SS to Sclock Edge Data Output Valid after SS Edge Lead Plastic Quad Flatpack Entire Data Sheet has been revisedOutline Dimensions Location Data Sheet changed from REV. a to REV. B
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