Analog Devices ADuC812 manual Efh, AQ1, AQ0 #ADC Clks, ADCCON1.1 T2C, ADCCON1.0 EXC

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ADuC812

ADCCON1 – (ADC Control SFR #1)

The ADCCON1 register controls conversion and acquisition times, hardware conversion modes and power-down modes as detailed below.

SFR Address:	EFH
SFR Power-On Default Value:	20H

MD1

MD0

CK1

CK0

AQ1

AQ0

T2C

EXC

				Table III. ADCCON1 SFR Bit Designations

Bit	Name	Description

ADCCON1.7	MD1	The mode bits (MD1, MD0) select the active operating mode of the ADC
ADCCON1.6	MD0	as follows:
		MD1	MD0 Active Mode
		0	0	ADC powered down.
		0	1	ADC normal mode
		1	0	ADC powered down if not executing a conversion cycle.
		1	1	ADC standby if not executing a conversion cycle.
		Note: In powered down mode the ADC VREF circuits are maintained on, whereas in power-down mode all
		ADC peripherals are powered down thus minimizing current consumption.
ADCCON1.5	CK1	The ADC clock divide bits (CK1, CK0) select the divide ratio for the master clock used to generate the
ADCCON1.4	CK0	ADC clock. A typical ADC conversion will require 17 ADC clocks. The divider ratio is selected
		as follows:
		CK1	CK0	MCLK Divider
		0	0	1
		0	1	2
		1	0	4
		1	1	8
ADCCON1.3	AQ1	The ADC acquisition select bits (AQ1, AQ0) select the time provided for the input track/hold amplifier
ADCCON1.2	AQ0	to acquire the input signal and are selected as follows:
		AQ1	AQ0 #ADC Clks
		0	0	1
		0	1	2
		1	0	4
		1	1	8
ADCCON1.1	T2C	The Timer 2 conversion bit (T2C) is set by the user to enable the Timer 2 over flow bit be used as
		the ADC convert start trigger input.
ADCCON1.0	EXC	The external trigger enable bit (EXC) is set by the user to allow the external Pin 23 (CONVST) to be
		used as the active low convert start input. This input should be an active low pulse (minimum pulse
		width >100 ns) at the required sample rate.

REV. B

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Contents General Description Functional Block DiagramADuC812 Table of ContentsCalibrated Endpoint ERRORS5 ADC Channel Specifications DC ACCURACY3Temperature SENSOR10 DAC Channel Specifications DC ACCURACY11FLASH/EE Memory Performance CHARACTERISTICS12 DAC AC CharacteristicsWatchdog Timer Characteristics Power Supply Monitor CharacteristicsDigital Outputs Power REQUIREMENTS14, 15Isource = 80 ∝A Isource = 20 ∝APIN Configuration Temperature Package Model Range Description OptionOrdering Guide Mnemonic Type Function DAC Specifications ADC SpecificationsTerminology Thus for a 12-bit converter, this is 74 dBMemory Organization ARCHITECTURE, Main FeaturesBit Name Description Special Function Registers Default Value SFR Address SFR NotesGeneral Overview ADC Circuit InformationADC Transfer Function Typical OperationAQ1 EFHAQ0 #ADC Clks ADCCON1.1 T2CCS3 CS2 CS1 CS0 CH# Location Name DescriptionBit Location Status Description Driving the A/D Converter Op Amp Model CharacteristicsTable VI. Some Single-Supply Op Amps ADC DMA Mode Configuring the ADCVoltage Reference Connections External memory must be preconfigured. This consists Where the ADC Results are to be written. This is done byDMAP. Dmal must be written to first, followed by Dmah and then by DmapByte Program Sequence SFR areaNonvolatile Flash Memory B9H EconEadrl C6HCommand Byte Command Mode Mode FDHRNG1 RNG0Resistor String DAC Functional Equivalent Using the D/A ConverterSource and Sink Current Capability with Vref = VDD = 3 PRE2 C0HPRE1 PRE0 PRE2 WDR1DCH DFHCMP PsmiOOH F8HIspi WcolSPR0 SPR1SPR1 SPR0 F7H2C Control Register I2CCONCompatible ON-CHIP Peripherals Pin Alternate FunctionT2CON TMOD, TconTR1 TF1TF0 TR0Mode 3 Two 8-Bit Timer/Counters TIMER/COUNTER 0 and 1 Operating ModesMode 1 16-Bit Timer/Counter TF2 C8HEXF2 RclkRclk or Tclk CAP2 TR2 ModeOFF SM1 SM0SM0 SM1 SM2Baud rate in Mode 0 is fixed CLK SmodRCAP2H RCAP2L Eadc A8HET2 ET1Source Vector Address Source Priority DescriptionClock Oscillator ADuC812 Hardware Design ConsiderationsExternal Memory Interface ADuC812-based system as well as during its normal power-on Down to 1.2 V or less. The timing diagram of illusLevel. The external POR circuit must be operational High it tracks the voltage on DVDD. These recommendationsIdle Mode Normal ModeVDD = 5 VDD = 3 Core NAs ⋅ Mclk +System Grounding Schemes Grounding and Board Layout RecommendationsOther Hardware Considerations In-Circuit Serial Download AccessEmbedded Serial Port Debugger ADSIM-Windows Simulator Quickstart Development SystemXTAL1 Width Low XTAL1 Period 83.33 62.5 1000XTAL1 Width High XTAL1 Rise TimeExternal Program Memory 12 MHz Variable Clock Parameter Min Max UnitExternal Data Memory Read Cycle External Data Memory Write Cycle Input Data Setup to Clock 300 2t CK + Output Data Setup to Clock 700 10t CKSerial Port Clock Cycle Time 12t CK Input Data Hold after ClockI2C-COMPATIBLE Interface Timing Parameter Min Max UnitParameter Min Typ Max Unit SPI Master Mode Timing Cpha =Data Output Setup before Sclock Edge 150 SS to Sclock Edge SPI Slave Mode Timing Cpha =SS High after Sclock Edge Data Output Valid after SS Edge Outline Dimensions Entire Data Sheet has been revisedLocation Data Sheet changed from REV. a to REV. B Lead Plastic Quad Flatpack